RFC locking and rate limit updates for i2c?

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On Tue, 22 Mar 2005 16:40:00 -0800, Philip Pokorny <ppokorny at penguincomputing.com> wrote:

>The ADM1026 and LM85 drivers should be requesting the semaphore on the 
     ^^^^^^^-- off my work list as it requires too much change
for an obvious fix, care to comment on partial patch?  

I stopped when I realised it had an odd data structure and fixing 
that is too invasive as I cannot go further than compile test.


Per register access locking achieves nothing for a read/modify/write 
cycle as another proces may change that register during the modify 
phase if i2c bus released.  

On one hand I've been told not to trust cache coherency with chip 
registers, thus implying read/modify/write cycle, which should take 
exclusive access to i2c bus for the read and writeback operations.

Does that clarify my query?

Thnaks,
Grant.



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