On Thu, Nov 04, 2021 at 09:08:41AM -0700, Dan Williams wrote: > Yes, atomic clear+write new data. The ability to atomic clear requires > either a CPU with the ability to overwrite cachelines without doing a > RMW cycle (MOVDIR64B), or it requires a device with a suitable > slow-path mailbox command like the one defined for CXL devices (see > section 8.2.9.5.4.3 Clear Poison in CXL 2.0). > > I don't know why you think these devices don't perform wear-leveling > with spare blocks? Because the interface looks so broken. But yes, apparently it's not the media management that is broken but just the inteface that fakes up byte level access. > All kernel accesses do use it. They either route to > pmem_copy_to_iter(), or like dm-writecache, call it directly. Do you > see a kernel path that does not use that helper? No, sorry. My knowledge is out of date. (nova does, but it is out of tree, and the lack of using copy_mc_to_kernel is the least of its problems)
