Hello.
On 10/03/16 19:14, web+oss@xxxxxxxxxxx wrote:
From: Alexandre Macabies <web+oss@xxxxxxxxxxx>
We set the TXNSECEN bit of register TXNCON to on when transmitting a
security-enabled frame, as described in section 3.12.2 of the MRF
datasheet.
SOB again.
Signed-off-by: Alexander Aring <aar@xxxxxxxxxxxxxx>
Reported-by: Alexandre Macabies <web+oss@xxxxxxxxxxx>
Tested-by: Alexandre Macabies <web+oss@xxxxxxxxxxx>
---
drivers/net/ieee802154/mrf24j40.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/net/ieee802154/mrf24j40.c b/drivers/net/ieee802154/mrf24j40.c
index 96814cf..bf11cbb 100644
--- a/drivers/net/ieee802154/mrf24j40.c
+++ b/drivers/net/ieee802154/mrf24j40.c
@@ -61,6 +61,7 @@
#define REG_TXBCON0 0x1A
#define REG_TXNCON 0x1B /* Transmit Normal FIFO Control */
#define BIT_TXNTRIG BIT(0)
+#define BIT_TXNSECEN BIT(1)
#define BIT_TXNACKREQ BIT(2)
#define REG_TXG1CON 0x1C
@@ -550,6 +551,9 @@ static void write_tx_buf_complete(void *context)
u8 val = BIT_TXNTRIG;
int ret;
+ if (ieee802154_is_secen(fc))
+ val |= BIT_TXNSECEN;
+
if (ieee802154_is_ackreq(fc))
val |= BIT_TXNACKREQ;
Code looks fine. With the SOB fixed you get my:
Reviewed-by: Stefan Schmidt <stefan@xxxxxxxxxxxxxxx>
regards
Stefan Schmidt
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