On Thu, 2012-02-23 at 11:16 +0100, Stanislaw Gruszka wrote:
> __iwl_clear_bit(trans, CSR_GP_CNTRL,
> CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
> + /*
> + * In above we are reading CSR_GP_CNTRL register, what will flush any
> + * previous writes, but still want write, which clear MAC_ACCESS_REQ
> + * bit, be performed on PCI bus before any other writes scheduled on
> + * different CPUs (after we drop reg_lock).
> + */
> + mmiowb();
> }
I changed this comment to the, imho, more readable
/*
* Above we read the CSR_GP_CNTRL register, which will flush
* any previous writes, but we need the write that clears the
* MAC_ACCESS_REQ bit to be performed before any other writes
* scheduled on different CPUs (after we drop reg_lock).
*/
johannes
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