On 04/19/2011 03:57 PM, Johannes Berg wrote:
I don't see how write flushing would be MIPS specific anyway? It's a function of the bus (PCI), not the host architecture, no?
Since I am not the original author of that piece of code, I had to make some inquiries, hence my non immediate response.
It turns out that the read-after-write construct was introduced in the code to ensure write order for certain Broadcom chips. Those chips are: bcm4706, bcm4716, bcm4717, bcm4718. All these chips contain a MIPS processor.
The #ifdef __mips__ in the code is broader than just those chips. The side effect is that other broadcom chips with a mips processor also execute the extra read, leading to some I/O overhead, which is acceptable.
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