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[PATCH V2 04/22] ath9k_hw: Configure pll control register accordingly for AR9340

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Vasanthakumar Thiagarajan wrote:
> Signed-off-by: Vasanthakumar Thiagarajan <vasanth@xxxxxxxxxxx>
> ---
>  drivers/net/wireless/ath/ath9k/hw.c  |   52 ++++++++++++++++++++++++++++++++--
>  drivers/net/wireless/ath/ath9k/hw.h  |    2 +-
>  drivers/net/wireless/ath/ath9k/phy.h |    3 ++
>  drivers/net/wireless/ath/ath9k/reg.h |    4 ++-
>  4 files changed, 56 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
> index 8c0364f..013ffba 100644
> --- a/drivers/net/wireless/ath/ath9k/hw.c
> +++ b/drivers/net/wireless/ath/ath9k/hw.c
> @@ -714,15 +714,48 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
>  			      AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
>  		udelay(1000);
>  
> -		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
> -			      AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);

Should this be removed ?

Sujith
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