On Tue, Apr 12, 2011 at 12:39:05PM +0200, Stanislaw Gruszka wrote:
> On Fri, Apr 08, 2011 at 08:30:30AM -0700, Wey-Yi Guy wrote:
> > + lctl = iwl_pcie_link_ctl(priv);
> > + if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
> > + PCI_CFG_LINK_CTRL_VAL_L1_EN) {
> > + /* L1-ASPM enabled; disable(!) L0S */
> > + iwl_set_bit(priv, CSR_GIO_REG,
> > + CSR_GIO_REG_VAL_L0S_ENABLED);
> > + IWL_DEBUG_POWER(priv, "L1 Enabled; Disabling L0S\n");
> > + } else {
> > + /* L1-ASPM disabled; enable(!) L0S */
We claim to enable L0S,
> > + iwl_clear_bit(priv, CSR_GIO_REG,
> > + CSR_GIO_REG_VAL_L0S_ENABLED);
but we clear CSR_GIO_REG_VAL_L0S_ENABLED bit, hmm ...
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