W dniu 7 kwietnia 2011 02:00 uÅytkownik George Kashperko <george@xxxxxxxxxxx> napisaÅ: > For PCI function description take a look at PCI specs or PCI > configuration space description (e. g. > http://en.wikipedia.org/wiki/PCI_configuration_space) > > Sorry for missleading short-ups, w11 - bcm80211 core, under two-head I > mean ssb/axi with two functional cores on same interconnect (like w11 > +w11, not a lot of these exists I guess). Also there were some b43+b44 > on single PCI ssb host and those where implemented as ssb interconnect > on multifunctional PCI host therefore providing separate access windows > for each function. > > Might I mussunderstood something (its late night here at my place) when > you where talking about using coreswitching involved for two drivers > therefore I remembered about those functions. Seems now you were talking > about chipcommon+b43 access sharing same window. > > As for core switching requirments for earlier SSB interconnects on PCI > hosts where there were no direct chipcommon access, that one can be > accomplished without spin_lock/mutex for b43 or b44 cores with proper > bus design. > > AXI doesn't need spinlocks/mutexes as both chipcommon and pci bridge are > available directly and b43 will be the only one requiring window access. Ahh, so while talking about 4 windows, I guess you counted fixes windows as well. That would be right, matching my knowledge. When asking question about amount of cores we may want to use simultaneously I didn't think about ChipCommon or PCIe. The real problem would be to support for example two 802.11 cores and one ethernet core at the same time. That gives us 3 cores while we have only 2 sliding windows. But I would not care for that too much for now. For the rest (PCI function) I have to sleep before reading specs ;) -- RafaÅ -- To unsubscribe from this list: send the line "unsubscribe linux-wireless" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
