On Thu, Mar 10, 2011 at 02:28:47PM +0530, Vasanthakumar Thiagarajan wrote:
> On Thu, Mar 10, 2011 at 06:05:01AM +0530, Felix Fietkau wrote:
> > +bool ath9k_hw_abort_tx_dma(struct ath_hw *ah)
> > +{
> > + int i, q;
> > +
> > + REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
> > +
> > + REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
> > + REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
> > + REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
> > +
> > + for (q = 0; q < AR_NUM_QCU; q++) {
> > + for (i = 1000; i > 0; i--) {
> > + if (!ath9k_hw_numtxpending(ah, q))
> > + break;
> > +
> > + udelay(5);
> > + }
> > + }
> > + if (!i)
> > + return false;
>
> Here the assumption looks like a reset would follow to configure
> those registers back, may be some comment will be useful.
>
Also a hw reset is not guaranteed to follow this,
call of ath_drain_all_txq() in .flush(), for ex.
Vasanth
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