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Re: wl1271 sdio timeouts on omap3

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On Wed, Nov 10, 2010 at 11:24 PM, Joerie de Gram <j.de.gram@xxxxxxxxx> wrote:
> clock:          25000000 Hz
> vdd:            7 (1.65 - 1.95 V)
> bus mode:       2 (push-pull)
> chip select:    0 (don't care)
> power mode:     2 (on)
> bus width:      2 (4 bits)
> timing spec:    0 (legacy)

seems good...

> It's a samsung GT-i8320 smartphone. Supposedly assembled correctly..

heh. yeah.

> If I stop it from setting maximum clock speed, it appears to run at
> 400 KHz and subsequently it (usually) manages to bring up the
> interface. AP scans seem to complete just fine too (although they
> yield no result, which is a different problem). It's still not
> entirely stable though (bringing the interface down and back up again
> results in another timeout).

Assuming that the hw is good (and if the proprietary driver runs ok
then it is) leaves us with mmc pins misconfiguration. Are you sure the
lines are pulled up ?

> Peeking at /dev/mem with the proprietary driver running suggests it
> runs at a (usual) 24 MHz mmc clock.

Yeah. but after passing the host controller divisor, it's exactly the
same as the 25Mhz you see with the the mainline driver.

>
> Joerie
>
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