On 08/22/2010 10:04 PM, Gábor Stefanik wrote:
+#define B43_MMIO_CLKCTL 0x1E0 /* clock control status */
Is it possible that all this stuff is completely bogus? All this clock control stuff you are trying to implement really looks like the standard SSB clock control which is already implemented in SSB. The clock control and status register of the chipcommon is 0x1E0. That "phy reset" stuff also mostly looks like you are reinventing the wheel for code that is already present. -- Greetings Michael. -- To unsubscribe from this list: send the line "unsubscribe linux-wireless" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
