Hi,
No, canot support this.
What happens if there is an interrupt immediately after the first
two reads - before the test on tsf_lower? - and thisinterrupt lasts longer
than 100us ? Most often, this is ok - until the interrupt happens at the
wrong time.
OR, there is a TSF merge event after the tsf_upper has been read, but
before the tsf_lower has been read? The tsf merge (which is done by the
hardware), adjusted both the high and low registers.
Derek.
On Sun, 28 Feb 2010, Benoit Papillault wrote:
+
+ tsf_upper = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
+ tsf_lower = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
+
+ if (tsf_lower < 100)
+ tsf_upper = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
+
ATH5K_TRACE(ah->ah_sc);
- return ath5k_hw_reg_read(ah, AR5K_TSF_L32) | (tsf << 32);
+ return (((u64)tsf_upper << 32) | tsf_lower);
}
/**
--
Derek Smithies Ph.D.
IndraNet Technologies Ltd.
ph +64 3 365 6485
Web: http://www.indranet-technologies.com/
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exactly one verb '*', which does exactly what I want at the moment."
--Larry Wall
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