On Wed, Nov 4, 2009 at 2:14 PM, Luis R. Rodriguez <mcgrof@xxxxxxxxxxxxxxxxxxxxxx> wrote: > On Wed, Nov 04, 2009 at 02:04:11PM -0800, Luis R. Rodriguez wrote: >> On Wed, Nov 4, 2009 at 2:00 PM, Matthew Wilcox <matthew@xxxxxx> wrote: >> > On Wed, Nov 04, 2009 at 01:52:30PM -0800, Luis R. Rodriguez wrote: >> >> > Even better: I just confirmation from our systems team that our legacy >> >> > devices and 11n PCI devices don't support MWR so I'll remove all that >> >> > cruft crap. >> >> >> >> I meant MWI of course. >> > >> > Yes, but they don't necessarily just use cacheline size for MWI ... some >> > devices use cacheline size for setting up data structures. Might be >> > worth just checking explicitly that they don't use the cacheline size >> > register for anything. >> >> Oh right -- so the typical Atheros hack for this is to check the cache >> line size, and if its 0 set it to L1_CACHE_BYTES. Then eventually read >> from PCI_CACHE_LINE_SIZE pci config to align the skb data. So what I >> was doing now is removing all this cruft and replacing it with a >> generic allocator for atheros drivers that aligns simply to the >> L1_CACHE_BYTES. Sound kosher? > > Something like this: I also checked with our systems team and it seems we do not rely on the PCI_CACHE_LINE_SIZE pci config to internally align data in the hardware itself. It that what you meant? Luis -- To unsubscribe from this list: send the line "unsubscribe linux-wireless" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
