2009/2/4 Nick Kossifidis <mickflemm@xxxxxxxxx>:
> 2009/2/4 Bob Copeland <me@xxxxxxxxxxxxxxx>:
>> On Tue, Feb 03, 2009 at 06:28:47PM +0200, Nick Kossifidis wrote:
>>> Nice catch ;-)
>>>
>>> Another difference i remembered is that we now don't set the TPC
>>> register to 3f (until we fix the whole tx power stuff). I'll try to
>>> reproduce this with my ar2425 as it turns it also has problems.
>>
>> And the winning hunk is:
>>
>> if (ah->ah_version != AR5K_AR5210) {
>> ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
>> - /* If we later allow tuning for this, store into sc structure */
>> - data = AR5K_TUNE_RSSI_THRES |
>> - AR5K_TUNE_BMISS_THRES << AR5K_RSSI_THR_BMISS_S;
>> - ath5k_hw_reg_write(ah, data, AR5K_RSSI_THR);
>> }
>>
>> (hmm, bmiss threshold, should've seen that before...)
>>
>> With that reverted from the rest of the patchset, I no longer get the
>> interrupt storm. I do seem to get an occasional lockup at association
>> time, but I haven't caught an oops for that yet. It could be unrelated.
>>
>
> O.K. i got that from legacy HAL. It first reads the register and if
> it's zeroed it sets to the default value of 0x781 (which is the same
> really, it's AR5K_TUNE_RSSI_THRES | AR5K_TUNE_BMISS_THRES <<
> AR5K_RSSI_THR_BMISS_S), if not it saves it and restores it after reset
> is done.
>
> So can you see why this
>
> /* Save RSSI thresholds (they 'll get zeroed from initvals) */
> rssi_thr = ath5k_hw_reg_read(ah, AR5K_RSSI_THR);
> /* If they are not set, set the default value */
> if (!rssi_thr)
> rssi_thr = AR5K_INIT_RSSI_THR;
>
> doesn't work ? What is the value of rssi_trh if not zero ?
>
Gotcha ;-)
rssi_thr: 0x40
I checked the docs and it seems this register is not changed by the
hw, so somewhere we write 0x40 on this register or something else
happens. I'll do some more research on that...
--
GPG ID: 0xD21DB2DB
As you read this post global entropy rises. Have Fun ;-)
Nick
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