QCOM PCIe controllers need to disable ASPM before initiating link
re-train. So as part of pre_bw_scale() disable ASPM and as part of
post_scale_bus_bw() enable ASPM back.
Update ICC & OPP votes based on the requested speed so that RPMh votes
get updated based on the speed.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx>
---
drivers/pci/controller/dwc/pcie-qcom.c | 49 ++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index b66c413f1e2b..a68e62422ff7 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1328,10 +1328,59 @@ static int qcom_pcie_set_icc_opp(struct qcom_pcie *pcie, int speed, int width)
return ret;
}
+static int qcom_pcie_scale_bw(struct dw_pcie_rp *pp, int speed)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct qcom_pcie *pcie = to_qcom_pcie(pci);
+ u32 offset, status, width;
+
+ offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+ status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
+
+ width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status);
+
+ return qcom_pcie_set_icc_opp(pcie, speed, width);
+}
+
+static int qcom_pcie_enable_disable_aspm(struct pci_dev *pdev, void *userdata)
+{
+ bool *enable = userdata;
+
+ /*
+ * QCOM controllers doesn't support link re-train with ASPM enabled.
+ * Disable ASPM as part of pre_bus_bw() and enable them back as
+ * part of post_bus_bw().
+ */
+ if (*enable)
+ pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL);
+ else
+ pci_disable_link_state_locked(pdev, PCIE_LINK_STATE_ALL);
+
+ return 0;
+}
+
+static void qcom_pcie_host_post_scale_bus_bw(struct dw_pcie_rp *pp, int current_speed)
+{
+ bool enable = true;
+
+ pci_walk_bus(pp->bridge->bus, qcom_pcie_enable_disable_aspm, &enable);
+ qcom_pcie_scale_bw(pp, current_speed);
+}
+
+static int qcom_pcie_host_pre_scale_bus_bw(struct dw_pcie_rp *pp, int target_speed)
+{
+ bool enable = false;
+
+ pci_walk_bus(pp->bridge->bus, qcom_pcie_enable_disable_aspm, &enable);
+ return qcom_pcie_scale_bw(pp, target_speed);
+}
+
static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
.init = qcom_pcie_host_init,
.deinit = qcom_pcie_host_deinit,
.post_init = qcom_pcie_host_post_init,
+ .pre_scale_bus_bw = qcom_pcie_host_pre_scale_bus_bw,
+ .post_scale_bus_bw = qcom_pcie_host_post_scale_bus_bw,
};
/* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */
--
2.34.1
