Bitterblue Smith <rtl8821cerfe2@xxxxxxxxx> wrote:
>
> Create the new module rtl8192d-common and move some code into it from
> rtl8192de. Now the rtl8192de driver (PCI) and the new rtl8192du driver
> (USB) can share some of the code.
>
> This is mostly the code that required little effort to make it
> shareable. There are a few more functions which they could share, with
> more changes.
>
> Add phy_iq_calibrate member to struct rtl_hal_ops to allow moving the
> TX power tracking code from dm.c.
>
> The other changes in this patch are adjusting whitespace, renaming some
> functions, making some arrays const, and making checkpatch.pl less
> unhappy.
>
> rtl8192de is compile-tested only. rtl8192d-common is tested with the
> new rtl8192du driver.
>
> Signed-off-by: Bitterblue Smith <rtl8821cerfe2@xxxxxxxxx>
Please find my comments below. Most should be fixed by patch 5/6, and
some should be in this patch.
> diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.h
> b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.h
> new file mode 100644
> index 000000000000..33b8ba363ca2
> --- /dev/null
> +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.h
> @@ -0,0 +1,39 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/* Copyright(c) 2009-2012 Realtek Corporation.*/
> +
> +#ifndef __RTL92D__FW_COMMON_H__
> +#define __RTL92D__FW_COMMON_H__
#define __RTL92D__FW_COMMON_H__
-->
#define __RTL92D_FW_COMMON_H__
#define __RTL92DE_HW_COMMON_H__
-->
#define __RTL92D_HW_COMMON_H__
#define __RTL92DE_TRX_COMMON_H__
-->
#define __RTL92D_TRX_COMMON_H__
[...]
> +static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo,
> + u8 *rom_content, bool autoloadfail)
> +{
> + u32 rfpath, eeaddr, group, offset1, offset2;
> + u8 i;
> +
> + memset(pwrinfo, 0, sizeof(struct txpower_info));
> + if (autoloadfail) {
> + for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
> + for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
> + if (group < CHANNEL_GROUP_MAX_2G) {
> + pwrinfo->cck_index[rfpath][group] =
> + EEPROM_DEFAULT_TXPOWERLEVEL_2G;
> + pwrinfo->ht40_1sindex[rfpath][group] =
> + EEPROM_DEFAULT_TXPOWERLEVEL_2G;
> + } else {
> + pwrinfo->ht40_1sindex[rfpath][group] =
> + EEPROM_DEFAULT_TXPOWERLEVEL_5G;
> + }
> + pwrinfo->ht40_2sindexdiff[rfpath][group] =
> + EEPROM_DEFAULT_HT40_2SDIFF;
> + pwrinfo->ht20indexdiff[rfpath][group] =
> + EEPROM_DEFAULT_HT20_DIFF;
> + pwrinfo->ofdmindexdiff[rfpath][group] =
> + EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
> + pwrinfo->ht40maxoffset[rfpath][group] =
> + EEPROM_DEFAULT_HT40_PWRMAXOFFSET;
> + pwrinfo->ht20maxoffset[rfpath][group] =
> + EEPROM_DEFAULT_HT20_PWRMAXOFFSET;
> + }
> + }
> + for (i = 0; i < 3; i++) {
> + pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI;
> + pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI;
> + }
> + return;
> + }
> +
> + /* Maybe autoload OK,buf the tx power index value is not filled.
> + * If we find it, we set it to default value.
> + */
> + for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
> + for (group = 0; group < CHANNEL_GROUP_MAX_2G; group++) {
> + eeaddr = EEPROM_CCK_TX_PWR_INX_2G + (rfpath * 3)
> + + group;
> + pwrinfo->cck_index[rfpath][group] =
> + (rom_content[eeaddr] == 0xFF) ?
> + (eeaddr > 0x7B ?
> + EEPROM_DEFAULT_TXPOWERLEVEL_5G :
> + EEPROM_DEFAULT_TXPOWERLEVEL_2G) :
> + rom_content[eeaddr];
With proper indent, it would be clearer:
for (group = 0; group < CHANNEL_GROUP_MAX_2G; group++) {
eeaddr = EEPROM_CCK_TX_PWR_INX_2G + (rfpath * 3) + group;
pwrinfo->cck_index[rfpath][group] =
rom_content[eeaddr] == 0xFF ?
(eeaddr > 0x7B ?
EEPROM_DEFAULT_TXPOWERLEVEL_5G :
EEPROM_DEFAULT_TXPOWERLEVEL_2G) :
rom_content[eeaddr];
}
> + }
> + }
> + for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
> + for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
> + offset1 = group / 3;
> + offset2 = group % 3;
> + eeaddr = EEPROM_HT40_1S_TX_PWR_INX_2G + (rfpath * 3) +
> + offset2 + offset1 * 21;
> + pwrinfo->ht40_1sindex[rfpath][group] =
> + (rom_content[eeaddr] == 0xFF) ? (eeaddr > 0x7B ?
> + EEPROM_DEFAULT_TXPOWERLEVEL_5G :
> + EEPROM_DEFAULT_TXPOWERLEVEL_2G) :
> + rom_content[eeaddr];
Similarly.
> + }
> + }
> + /* These just for 92D efuse offset. */
> + for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
> + for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
> + int base1 = EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G;
> +
> + offset1 = group / 3;
> + offset2 = group % 3;
> +
> + if (rom_content[base1 + offset2 + offset1 * 21] != 0xFF)
> + pwrinfo->ht40_2sindexdiff[rfpath][group] =
> + (rom_content[base1 +
> + offset2 + offset1 * 21] >> (rfpath * 4))
> + & 0xF;
it would be more readable to move '& 0xF' to tail of previous line
pwrinfo->ht40_2sindexdiff[rfpath][group] =
(rom_content[base1 +
offset2 + offset1 * 21] >> (rfpath * 4)) & 0xF;
> + else
> + pwrinfo->ht40_2sindexdiff[rfpath][group] =
> + EEPROM_DEFAULT_HT40_2SDIFF;
> + if (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G + offset2
> + + offset1 * 21] != 0xFF)
Splitting index of [] into two lines would hard to read.
Use a local varialbe.
(a blank line)
offset = EEPROM_HT20_TX_PWR_INX_DIFF_2G + offset2 + offset1 * 21;
if (rom_content[offset] != 0xFF)
We can apply this patter across this function.
> + pwrinfo->ht20indexdiff[rfpath][group] =
> + (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G
> + + offset2 + offset1 * 21] >> (rfpath * 4))
> + & 0xF;
> + else
> + pwrinfo->ht20indexdiff[rfpath][group] =
> + EEPROM_DEFAULT_HT20_DIFF;
> + if (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G + offset2
> + + offset1 * 21] != 0xFF)
> + pwrinfo->ofdmindexdiff[rfpath][group] =
> + (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G
> + + offset2 + offset1 * 21] >> (rfpath * 4))
> + & 0xF;
> + else
> + pwrinfo->ofdmindexdiff[rfpath][group] =
> + EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
> + if (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G + offset2
> + + offset1 * 21] != 0xFF)
> + pwrinfo->ht40maxoffset[rfpath][group] =
> + (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G
> + + offset2 + offset1 * 21] >> (rfpath * 4))
> + & 0xF;
> + else
> + pwrinfo->ht40maxoffset[rfpath][group] =
> + EEPROM_DEFAULT_HT40_PWRMAXOFFSET;
> + if (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + offset2
> + + offset1 * 21] != 0xFF)
> + pwrinfo->ht20maxoffset[rfpath][group] =
> + (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G +
> + offset2 + offset1 * 21] >> (rfpath * 4)) &
> + 0xF;
> + else
> + pwrinfo->ht20maxoffset[rfpath][group] =
> + EEPROM_DEFAULT_HT20_PWRMAXOFFSET;
> + }
> + }
> + if (rom_content[EEPROM_TSSI_A_5G] != 0xFF) {
> + /* 5GL */
> + pwrinfo->tssi_a[0] = rom_content[EEPROM_TSSI_A_5G] & 0x3F;
> + pwrinfo->tssi_b[0] = rom_content[EEPROM_TSSI_B_5G] & 0x3F;
> + /* 5GM */
> + pwrinfo->tssi_a[1] = rom_content[EEPROM_TSSI_AB_5G] & 0x3F;
> + pwrinfo->tssi_b[1] =
> + (rom_content[EEPROM_TSSI_AB_5G] & 0xC0) >> 6 |
> + (rom_content[EEPROM_TSSI_AB_5G + 1] & 0x0F) << 2;
> + /* 5GH */
> + pwrinfo->tssi_a[2] = (rom_content[EEPROM_TSSI_AB_5G + 1] &
> + 0xF0) >> 4 |
> + (rom_content[EEPROM_TSSI_AB_5G + 2] & 0x03) << 4;
> + pwrinfo->tssi_b[2] = (rom_content[EEPROM_TSSI_AB_5G + 2] &
> + 0xFC) >> 2;
> + } else {
> + for (i = 0; i < 3; i++) {
> + pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI;
> + pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI;
> + }
> + }
> +}
> +
[...]
> +static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw)
> +{
> + struct rtl_priv *rtlpriv = rtl_priv(hw);
> + struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
> + struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
> + int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID,
> + EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR_MAC0_92D,
> + EEPROM_CHANNEL_PLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
> + COUNTRY_CODE_WORLD_WIDE_13};
> + int i;
> + u16 usvalue;
> + u8 *hwinfo;
> +
> + hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
> + if (!hwinfo)
> + return;
> +
> + if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
> + goto exit;
> +
> + _rtl92de_efuse_update_chip_version(hw);
> + _rtl92de_read_macphymode_and_bandtype(hw, hwinfo);
> +
> + /* Read Permanent MAC address for 2nd interface */
> + if (rtlhal->interfaceindex != 0) {
> + for (i = 0; i < 6; i += 2) {
> + usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC1_92D + i];
> + *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue;
Copying u16 looks weird. I guess it would like to swap bytes (endian problem).
At least it should be '__le16' or '__be16' because hwinfo[] is from efuse.
> + }
> + }
> + rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR,
> + rtlefuse->dev_addr);
> + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
> + _rtl92de_read_txpower_info(hw, rtlefuse->autoload_failflag, hwinfo);
> +
> + /* Read Channel Plan */
> + switch (rtlhal->bandset) {
> + case BAND_ON_2_4G:
> + rtlefuse->channel_plan = COUNTRY_CODE_TELEC;
> + break;
> + case BAND_ON_5G:
> + rtlefuse->channel_plan = COUNTRY_CODE_FCC;
> + break;
> + case BAND_ON_BOTH:
> + rtlefuse->channel_plan = COUNTRY_CODE_FCC;
> + break;
> + default:
> + rtlefuse->channel_plan = COUNTRY_CODE_FCC;
> + break;
> + }
> + rtlefuse->txpwr_fromeprom = true;
> +exit:
> + kfree(hwinfo);
> +}
> +
[...]
> +static void rtl92d_phy_set_io(struct ieee80211_hw *hw)
> +{
> + struct rtl_priv *rtlpriv = rtl_priv(hw);
> + struct dig_t *de_digtable = &rtlpriv->dm_digtable;
> + struct rtl_phy *rtlphy = &rtlpriv->phy;
> +
> + rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
> + "--->Cmd(%#x), set_io_inprogress(%d)\n",
> + rtlphy->current_io_type, rtlphy->set_io_inprogress);
a blank line
> + switch (rtlphy->current_io_type) {
> + case IO_CMD_RESUME_DM_BY_SCAN:
> + de_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
> + rtl92d_dm_write_dig(hw);
> + rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
> + break;
> + case IO_CMD_PAUSE_DM_BY_SCAN:
> + rtlphy->initgain_backup.xaagccore1 = de_digtable->cur_igvalue;
> + de_digtable->cur_igvalue = 0x37;
> + rtl92d_dm_write_dig(hw);
> + break;
> + default:
> + pr_err("switch case %#x not processed\n",
> + rtlphy->current_io_type);
> + break;
> + }
a blank line
> + rtlphy->set_io_inprogress = false;
> + rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n",
> + rtlphy->current_io_type);
> +}
> +
> +bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
> +{
> + struct rtl_priv *rtlpriv = rtl_priv(hw);
> + struct rtl_phy *rtlphy = &rtlpriv->phy;
> + bool postprocessing = false;
> +
> + rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
> + "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
> + iotype, rtlphy->set_io_inprogress);
a blank line
> + do {
> + switch (iotype) {
> + case IO_CMD_RESUME_DM_BY_SCAN:
> + rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
> + "[IO CMD] Resume DM after scan\n");
> + postprocessing = true;
> + break;
> + case IO_CMD_PAUSE_DM_BY_SCAN:
> + rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
> + "[IO CMD] Pause DM before scan\n");
> + postprocessing = true;
> + break;
> + default:
> + pr_err("switch case %#x not processed\n",
> + iotype);
> + break;
> + }
> + } while (false);
a blank line
> + if (postprocessing && !rtlphy->set_io_inprogress) {
> + rtlphy->set_io_inprogress = true;
> + rtlphy->current_io_type = iotype;
> + } else {
> + return false;
> + }
a blank line
> + rtl92d_phy_set_io(hw);
> + rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype);
> + return true;
> +}
> +EXPORT_SYMBOL_GPL(rtl92d_phy_set_io_cmd);
> +
[...]
> +
> +void rtl92d_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
> +{
> + struct rtl_priv *rtlpriv = rtl_priv(hw);
> + struct rtl_phy *rtlphy = &rtlpriv->phy;
> + u8 rfpath;
> +
> + switch (bandwidth) {
> + case HT_CHANNEL_WIDTH_20:
> + for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
> + rtlphy->rfreg_chnlval[rfpath] = ((rtlphy->rfreg_chnlval
> + [rfpath] & 0xfffff3ff) | 0x0400);
[] should be together with variables
rtlphy->rfreg_chnlval[rfpath] =
((rtlphy->rfreg_chnlval[rfpath] & 0xfffff3ff) | 0x0400);
> + rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) |
> + BIT(11), 0x01);
> +
> + rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD,
> + "20M RF 0x18 = 0x%x\n",
> + rtlphy->rfreg_chnlval[rfpath]);
> + }
> +
> + break;
> + case HT_CHANNEL_WIDTH_20_40:
> + for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
> + rtlphy->rfreg_chnlval[rfpath] =
> + ((rtlphy->rfreg_chnlval[rfpath] & 0xfffff3ff));
> + rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) | BIT(11),
> + 0x00);
> + rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD,
> + "40M RF 0x18 = 0x%x\n",
> + rtlphy->rfreg_chnlval[rfpath]);
> + }
> + break;
> + default:
> + pr_err("unknown bandwidth: %#X\n", bandwidth);
> + break;
> + }
> +}
[...]
> +
> +static void _rtl92d_phy_get_power_base(struct ieee80211_hw *hw,
> + u8 *ppowerlevel, u8 channel,
> + u32 *ofdmbase, u32 *mcsbase)
> +{
> + struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
> + struct rtl_priv *rtlpriv = rtl_priv(hw);
> + struct rtl_phy *rtlphy = &rtlpriv->phy;
> + u32 powerbase0, powerbase1;
> + u8 legacy_pwrdiff, ht20_pwrdiff;
> + u8 i, powerlevel[2];
> +
> + for (i = 0; i < 2; i++) {
> + powerlevel[i] = ppowerlevel[i];
> + legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1];
> + powerbase0 = powerlevel[i] + legacy_pwrdiff;
> + powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) |
> + (powerbase0 << 8) | powerbase0;
powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) |
(powerbase0 << 8) | powerbase0;
> + *(ofdmbase + i) = powerbase0;
> + RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
> + " [OFDM power base index rf(%c) = 0x%x]\n",
> + i == 0 ? 'A' : 'B', *(ofdmbase + i));
> + }
> +
> + for (i = 0; i < 2; i++) {
> + if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
> + ht20_pwrdiff = rtlefuse->txpwr_ht20diff[i][channel - 1];
> + powerlevel[i] += ht20_pwrdiff;
> + }
> + powerbase1 = powerlevel[i];
> + powerbase1 = (powerbase1 << 24) | (powerbase1 << 16) |
> + (powerbase1 << 8) | powerbase1;
> + *(mcsbase + i) = powerbase1;
> + RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
> + " [MCS power base index rf(%c) = 0x%x]\n",
> + i == 0 ? 'A' : 'B', *(mcsbase + i));
> + }
> +}
> +
