> -----Original Message----- > From: Ali Ghandour <gandour.ali@xxxxxxxxx> > Sent: Tuesday, December 5, 2023 2:13 PM > To: Ping-Ke Shih <pkshih@xxxxxxxxxxx> > Cc: linux-wireless@xxxxxxxxxxxxxxx > Subject: Re: Lenovo LOQ rtw_8852be > > > > > > > > $ lspci -tv > > > > > > -[0000:00]-+-00.0 Intel Corporation Device a715 > > > >> Can I know the type of your platoform Lenovo LOQ? Is it a regular notebook computer? > > > > > > LOQ 15IRH8 - Type 82XV > > > I am using a dual boot with Windows and Ubuntu 22.04 > > > > I still can't find information about the device a715 that I also can't find > > this ID in kernel source code. I will dig kernel further when I have free time. > > > According to the specs: > 1x 13th Generation Intel Core i7-13620H Processor(Core i7-13620H) > I have found the ID in kernel: arch/x86/events/intel/uncore_snb.c:101:#define PCI_DEVICE_ID_INTEL_RPL_15_IMC 0xA715 But honestly I'm not familiar with PCI. I'll continue to dig to see if I can find something... > > > > > > > > > > >> The PCI EXT capabilities locate from 100h. Not sure if host controller driver limits to display them? > > > I did not get your question. Can you say it again please? > > > > I meant offset 100h of PCI configuration space is a standard area [1]. > > > > "PCI Express extends the Configuration Space to 4096 bytes per Function as compared to 256 bytes > > allowed by PCI Local Bus Specification. PCI Express Configuration Space is divided into a PCI 3.0 > > compatible region, which consists of the first 256 bytes of a Function’s Configuration Space, and a > > PCI Express Extended Configuration Space which consists of the remaining Configuration Space > > 5 (see Figure 7-3)." > > > > I don't know why the PCI controller in your platform doesn't recognize the region, > > and then _possibly_ cause driver failed to access 719h. > > > > > > [1] https://blog.csdn.net/huangkangying/article/details/50570612 > > According to the specs: > 2 x M.2 (PCI Express 4.0 x4) (1 free) > 512 GB SSD M.2 2242 PCIe 4.0 x4 - NVM Express (NVMe) > and I have actually inserted a second SSD myself > > Is the driver compatible with PCI 4.0? I think PCI should be backward compatible to older devices. I did trace PCI code and found pci_dev->cfg_size limit the access, so please try below hack patch in driver and see pci_dev->cfg_size in your platform. @@ -2111,6 +2111,11 @@ static int rtw89_pci_auto_refclk_cal(struct rtw89_dev *rtwdev, bool autook_en) u8 val8, bdr_ori; bool l1_flag = false; int ret = 0; + struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; + struct pci_dev *pdev = rtwpci->pdev; + + printk("pdev->cfg_size=%d\n", pdev->cfg_size); // in my computer, this is 4096 already + pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; // 4096 if (chip_id != RTL8852B && chip_id != RTL8851B) return 0; Ping-Ke
