On 01/12/2022 16:55, Jun ASAKA wrote: > Fixing "Path A RX IQK failed" and "Path B RX IQK failed" > issues for rtl8192eu chips by replacing the arguments with > the ones in the updated official driver as shown below. > 1. https://github.com/Mange/rtl8192eu-linux-driver > 2. vendor driver version: 5.6.4 > > Tested-by: Jun ASAKA <JunASAKA@xxxxxxxxxxxxx> > Signed-off-by: Jun ASAKA <JunASAKA@xxxxxxxxxxxxx> > --- > v3: > - add detailed info about the newer version this patch used. > - no functional update. > --- > .../realtek/rtl8xxxu/rtl8xxxu_8192e.c | 76 +++++++++++++------ > 1 file changed, 54 insertions(+), 22 deletions(-) > > diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c > index b06508d0cd..82346500f2 100644 > --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c > +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c > @@ -734,6 +734,12 @@ static int rtl8192eu_iqk_path_a(struct rtl8xxxu_priv *priv) > */ > rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); > rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00180); > + > + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); > + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); > + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); > + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0x07f77); > +> rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); > > /* Path A IQK setting */ > @@ -779,11 +785,16 @@ static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) > rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); > rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); > rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); > - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf117b); > + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173); > + > + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); > + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); > + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); > + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf1173); > > /* PA/PAD control by 0x56, and set = 0x0 */ > rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980); > - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000); > + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x511e0); > > /* Enter IQK mode */ > rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); > @@ -798,14 +809,14 @@ static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) > rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); > rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); > > - rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f); > - rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160c1f); > + rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x8216031f); > + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x6816031f); > > /* LO calibration setting */ > rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); > > /* One shot, path A LOK & IQK */ > - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); > + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); > rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); > > mdelay(10); > @@ -836,11 +847,16 @@ static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) > rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); > rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); > rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); > - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ffa); > + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2); > + > + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); > + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); > + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); > + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ff2); > > /* PA/PAD control by 0x56, and set = 0x0 */ > rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980); > - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000); > + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x510e0); > > /* Enter IQK mode */ > rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); > @@ -854,14 +870,14 @@ static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) > rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); > rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); > > - rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f); > - rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c1f); > + rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821608ff); > + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281608ff); > > /* LO calibration setting */ > rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891); > > /* One shot, path A LOK & IQK */ > - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); > + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); > rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); > > mdelay(10); > @@ -891,22 +907,28 @@ static int rtl8192eu_iqk_path_b(struct rtl8xxxu_priv *priv) > > rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); > rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00180); > - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); > > - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); > + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); > + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x20000); > + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); > + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0x07f77); > + > rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); > > + // rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); > + // rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); > + This commented code is not needed. > /* Path B IQK setting */ > rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); > rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); > rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); > rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); > > - rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x821403e2); > + rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140303); > rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160000); > > /* LO calibration setting */ > - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00492911); > + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); > > /* One shot, path A LOK & IQK */ > rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); > @@ -942,11 +964,16 @@ static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv) > rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); > rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); > rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); > - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf117b); > + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf1173); > + > + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); > + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); > + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); > + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173); > > /* PA/PAD control by 0x56, and set = 0x0 */ > rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980); > - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x51000); > + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x511e0); > > /* Enter IQK mode */ > rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); > @@ -961,8 +988,8 @@ static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv) > rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); > rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); > > - rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82160c1f); > - rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160c1f); > + rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x8216031f); > + rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x6816031f); > > /* LO calibration setting */ > rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); > @@ -1002,11 +1029,16 @@ static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv) > rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); > rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); > rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); > - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ffa); > + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ff2); > + > + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); > + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); > + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); > + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ff2); These four lines you added here should be using RF_A. > > /* PA/PAD control by 0x56, and set = 0x0 */ > rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980); > - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x51000); > + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x510e0); > > /* Enter IQK mode */ > rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); > @@ -1020,8 +1052,8 @@ static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv) > rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); > rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x18008c1c); > > - rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f); > - rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c1f); > + rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821608ff); > + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281608ff); > > /* LO calibration setting */ > rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891); The rest of your changes look okay to me.
