On 25/10/2022 06:46, Ping-Ke Shih wrote:
>
>
>> -----Original Message-----
>> From: Bitterblue Smith <rtl8821cerfe2@xxxxxxxxx>
>> Sent: Tuesday, October 25, 2022 4:55 AM
>> To: linux-wireless@xxxxxxxxxxxxxxx
>> Cc: Jes Sorensen <Jes.Sorensen@xxxxxxxxx>
>> Subject: [PATCH v2 2/5] wifi: rtl8xxxu: Fix the CCK RSSI calculation
>>
>> The CCK RSSI calculation is incorrect for the RTL8723BU, RTL8192EU,
>> and RTL8188FU. Add new functions for these chips with code copied from
>> their vendor drivers. Use the old code only for the RTL8723AU and
>> RTL8192CU.
>>
>> I didn't notice any difference in the reported signal strength with my
>> RTL8188FU, but I didn't look very hard either.
>>
>> Signed-off-by: Bitterblue Smith <rtl8821cerfe2@xxxxxxxxx>
>> ---
>> v2:
>> - No change.
>> ---
>> .../net/wireless/realtek/rtl8xxxu/rtl8xxxu.h | 3 ++
>> .../realtek/rtl8xxxu/rtl8xxxu_8188f.c | 32 ++++++++++++++++
>> .../realtek/rtl8xxxu/rtl8xxxu_8192c.c | 1 +
>> .../realtek/rtl8xxxu/rtl8xxxu_8192e.c | 23 +++++++++++
>> .../realtek/rtl8xxxu/rtl8xxxu_8723a.c | 23 +++++++++++
>> .../realtek/rtl8xxxu/rtl8xxxu_8723b.c | 29 ++++++++++++++
>> .../wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 38 ++++++++++++-------
>> 7 files changed, 135 insertions(+), 14 deletions(-)
>>
>
> [...]
>
>> diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
>> b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
>> index 86a3457fd951..7023f6accda7 100644
>> --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
>> +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
>> @@ -4325,6 +4325,29 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
>> val32 &= 0xfff00fff;
>> val32 |= 0x0007e000;
>> rtl8xxxu_write32(priv, REG_AFE_MISC, val32);
>> +
>> + /*
>> + * 0x824[9] = 0x82C[9] = 0xA80[7] those registers setting
>> + * should be equal or CCK RSSI report may be incorrect
>> + */
>> + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
>> + priv->cck_agc_report_type = val32 & FPGA0_HSSI_PARM2_CCK_HIGH_PWR;
>> +
>> + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_HSSI_PARM2);
>> + if (priv->cck_agc_report_type != (bool)(val32 & FPGA0_HSSI_PARM2_CCK_HIGH_PWR)) {
>> + if (priv->cck_agc_report_type)
>> + val32 |= FPGA0_HSSI_PARM2_CCK_HIGH_PWR;
>> + else
>> + val32 &= ~FPGA0_HSSI_PARM2_CCK_HIGH_PWR;
>> + rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM2, val32);
>> + }
>> +
>> + val32 = rtl8xxxu_read32(priv, 0xa80);
>> + if (priv->cck_agc_report_type)
>> + val32 |= BIT(7);
>> + else
>> + val32 &= ~BIT(7);
>
> We can give a name to 0xA80[7]:
>
> #define REG_AGC_RPT 0x0a80
> #define AGC_RTP_CCK BIT(7)
>
>
Thanks, I'll add it.
