On 24/05/22 13:39, Claudiu Beznea - M18063 wrote: > Hi, Ajay, > > On 23.05.2022 17:09, Ajay Kathat - I15481 wrote: >> From: Ajay Singh <ajay.kathat@xxxxxxxxxxxxx> >> >> For power-up sequence, WILC expects RESET set to high 5ms after making >> chip_en(enable) so corrected chip power-up sequence by making RESET high. >> For Power-Down sequence, the correct sequence make RESET and CHIP_EN low >> without any extra delay. >> >> Signed-off-by: Ajay Singh <ajay.kathat@xxxxxxxxxxxxx> > Does this need a fixes tag? Yes, I will add the Fixes tag and send the v3 series. Regards, Ajay
