From: Viktor Barna <viktor.barna@xxxxxxxxxx>
(Part of the split. Please, take a look at the cover letter for more
details).
Signed-off-by: Viktor Barna <viktor.barna@xxxxxxxxxx>
---
drivers/net/wireless/celeno/cl8k/dfs.h | 146 +++++++++++++++++++++++++
1 file changed, 146 insertions(+)
create mode 100644 drivers/net/wireless/celeno/cl8k/dfs.h
diff --git a/drivers/net/wireless/celeno/cl8k/dfs.h b/drivers/net/wireless/celeno/cl8k/dfs.h
new file mode 100644
index 000000000000..a252844f854b
--- /dev/null
+++ b/drivers/net/wireless/celeno/cl8k/dfs.h
@@ -0,0 +1,146 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/* Copyright(c) 2019-2022, Celeno Communications Ltd. */
+
+#ifndef CL_DFS_H
+#define CL_DFS_H
+
+#include <linux/types.h>
+#include <linux/spinlock.h>
+
+#include "debug.h"
+
+#define CL_DFS_MAX_TBL_LINE 11 /* Radar Table Max Line */
+#define CL_DFS_PULSE_BUF_SIZE 64 /* Radar Pulse buffer size */
+#define CL_DFS_PULSE_BUF_MASK 0x03F /* Radar Pulse buffer cyclic mask */
+#define CL_DFS_PULSE_WINDOW 100 /* Radar Pulse search window [ms] */
+#define CL_DFS_MIN_PULSE_TRIG 1 /* Minimum Pulse trigger num */
+#define CL_DFS_LONG_MIN_WIDTH 20 /* Min Long Pulse Width */
+#define CL_DFS_LONG_FALSE_WIDTH 10 /* Low width signals indicates of false detections */
+#define CL_DFS_LONG_FALSE_IND 6 /* False indication while searching for long sequence */
+#define CL_DFS_STAGGERED_CHEC_LEN 4 /* Staggered check length */
+#define CL_DFS_CONCEAL_CNT 10 /* Maximum concealed pulses search */
+#define CL_DFS_MIN_FREQ 5250 /* Min DFS frequency */
+#define CL_DFS_MAX_FREQ 5725 /* Max DFS frequency */
+
+enum cl_radar_waveform {
+ RADAR_WAVEFORM_SHORT,
+ RADAR_WAVEFORM_LONG,
+ RADAR_WAVEFORM_STAGGERED,
+ RADAR_WAVEFORM_SEVERE
+};
+
+struct cl_radar_type {
+ u8 id;
+ s32 min_width;
+ s32 max_width;
+ s32 tol_width;
+ s32 min_pri;
+ s32 max_pri;
+ s32 tol_pri;
+ s32 tol_freq;
+ u8 min_burst;
+ u8 ppb;
+ u8 trig_count;
+ enum cl_radar_waveform waveform;
+};
+
+/* Number of pulses in a radar event structure */
+#define RADAR_PULSE_MAX 4
+
+/*
+ * Structure used to store information regarding
+ * E2A radar events in the driver
+ */
+struct cl_radar_elem {
+ struct cl_radar_pulse_array *radarbuf_ptr;
+ dma_addr_t dma_addr;
+};
+
+/* Bit mapping inside a radar pulse element */
+struct cl_radar_pulse {
+ u64 freq : 8;
+ u64 fom : 8;
+ u64 len : 8; /* Pulse length timer */
+ u64 measure_cnt : 2; /* Measure count */
+ u64 rsv1 : 6; /* Reserve1 */
+ u64 rep : 16; /* PRI */
+ u64 rsv2 : 16; /* Reserve2 */
+};
+
+/* Definition of an array of radar pulses */
+struct cl_radar_pulse_array {
+ /* Buffer containing the radar pulses */
+ u64 pulse[RADAR_PULSE_MAX];
+ /* Number of valid pulses in the buffer */
+ u32 cnt;
+};
+
+struct cl_radar_queue_elem {
+ struct list_head list;
+ struct cl_hw *cl_hw;
+ struct cl_radar_elem radar_elem;
+ unsigned long time;
+};
+
+struct cl_radar_queue {
+ struct list_head head;
+ spinlock_t lock;
+};
+
+struct cl_dfs_pulse {
+ s32 freq : 8; /* Radar Frequency offset [units of 4MHz] */
+ u32 fom : 8; /* Figure of Merit */
+ u32 width : 8; /* Pulse Width [units of 2 micro sec] */
+ u32 occ : 1; /* OCC indication for Primary/Secondary channel */
+ u32 res1 : 7; /* Reserve */
+ u32 pri : 16; /* Pulse Repetition Frequency */
+ u32 res2 : 16;
+ unsigned long time; /* Pulse Receive Time */
+};
+
+struct cl_dfs_db {
+ bool en;
+ enum cl_dbg_level dbg_lvl;
+ enum nl80211_dfs_regions dfs_standard;
+ struct {
+ bool started;
+ bool requested;
+ } cac;
+ u8 long_pulse_count;
+ u32 last_long_pulse_ts;
+ u8 short_pulse_count;
+ u8 long_pri_match_count;
+ u8 min_pulse_eeq;
+ u8 buf_idx;
+ u8 radar_type_cnt;
+ u16 search_window;
+ u16 max_interrupt_diff;
+ u16 remain_cac_time;
+ u32 pulse_cnt;
+ struct cl_radar_type *radar_type;
+ struct cl_dfs_pulse dfs_pulse[CL_DFS_PULSE_BUF_SIZE];
+ struct cl_dfs_pulse pulse_buffer[CL_DFS_PULSE_BUF_SIZE];
+};
+
+void cl_dfs_init(struct cl_hw *cl_hw);
+void cl_dfs_reinit(struct cl_hw *cl_hw);
+void cl_dfs_start(struct cl_hw *cl_hw);
+void cl_dfs_recovery(struct cl_hw *cl_hw);
+bool cl_dfs_pulse_process(struct cl_hw *cl_hw, struct cl_radar_pulse *pulse, u8 pulse_cnt,
+ unsigned long time);
+bool __must_check cl_dfs_is_in_cac(struct cl_hw *cl_hw);
+bool __must_check cl_dfs_requested_cac(struct cl_hw *cl_hw);
+bool __must_check cl_dfs_radar_listening(struct cl_hw *cl_hw);
+void cl_dfs_request_cac(struct cl_hw *cl_hw, bool should_do);
+void cl_dfs_force_cac_start(struct cl_hw *cl_hw);
+void cl_dfs_force_cac_end(struct cl_hw *cl_hw);
+void cl_dfs_radar_listen_start(struct cl_hw *cl_hw);
+void cl_dfs_radar_listen_end(struct cl_hw *cl_hw);
+
+void cl_radar_init(struct cl_hw *cl_hw);
+void cl_radar_push(struct cl_hw *cl_hw, struct cl_radar_elem *radar_elem);
+void cl_radar_tasklet_schedule(struct cl_hw *cl_hw);
+void cl_radar_flush(struct cl_hw *cl_hw);
+void cl_radar_close(struct cl_hw *cl_hw);
+
+#endif /* CL_DFS_H */
--
2.36.1
