From: Viktor Barna <viktor.barna@xxxxxxxxxx>
(Part of the split. Please, take a look at the cover letter for more
details).
Signed-off-by: Viktor Barna <viktor.barna@xxxxxxxxxx>
---
drivers/net/wireless/celeno/cl8k/power.h | 90 ++++++++++++++++++++++++
1 file changed, 90 insertions(+)
create mode 100644 drivers/net/wireless/celeno/cl8k/power.h
diff --git a/drivers/net/wireless/celeno/cl8k/power.h b/drivers/net/wireless/celeno/cl8k/power.h
new file mode 100644
index 000000000000..cd1d36492317
--- /dev/null
+++ b/drivers/net/wireless/celeno/cl8k/power.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/* Copyright(c) 2019-2022, Celeno Communications Ltd. */
+
+#ifndef CL_POWER_H
+#define CL_POWER_H
+
+#define NUM_POWER_WORDS 256
+#define POWER_MIN_DB -10
+#define POWER_MIN_DB_Q1 (POWER_MIN_DB << 1)
+#define POWER_MIN_DB_Q8 (POWER_MIN_DB << 8)
+#define POWER_OFFSET_RES 4
+
+struct cl_power_table_data {
+ u8 conv_table[NUM_POWER_WORDS];
+};
+
+struct cl_power_table_info {
+ struct cl_power_table_data *data;
+ u32 dma_addr;
+};
+
+#define PWR_TBL_HE_BF_SIZE (WRS_SS_MAX + 1)
+#define PWR_TBL_VHT_BF_SIZE WRS_SS_MAX
+
+/*
+ * Structure containing the power tables
+ * All values are in resolution of 0.5dBm
+ */
+struct cl_pwr_tables {
+ /* Regular Tx */
+ s8 ant_pwr_he[CHNL_BW_MAX][WRS_MCS_MAX_HE][PWR_TBL_HE_BF_SIZE];
+ s8 ant_pwr_ht_vht[CHNL_BW_MAX][WRS_MCS_MAX_VHT][PWR_TBL_VHT_BF_SIZE];
+ s8 ant_pwr_ofdm[WRS_MCS_MAX_OFDM];
+ s8 ant_pwr_cck[WRS_MCS_MAX_CCK];
+ /* VNS */
+ s8 ant_pwr_vns_he;
+ s8 ant_pwr_vns_ht_vht;
+ s8 ant_pwr_vns_ofdm;
+ s8 ant_pwr_vns_cck;
+ /* Auto response */
+ s8 pwr_auto_resp_he[WRS_MCS_MAX_HE];
+ s8 pwr_auto_resp_ht_vht[WRS_MCS_MAX_VHT];
+ s8 pwr_auto_resp_ofdm[WRS_MCS_MAX_OFDM];
+ s8 pwr_auto_resp_cck[WRS_MCS_MAX_CCK];
+ /* Auto response VNS */
+ s8 pwr_auto_resp_vns_he;
+ s8 pwr_auto_resp_vns_ht_vht;
+ s8 pwr_auto_resp_vns_ofdm;
+ s8 pwr_auto_resp_vns_cck;
+};
+
+struct cl_power_db {
+ u8 curr_percentage;
+ s8 curr_offset;
+ /* Used to validate margins of MAC power */
+ s8 bw_factor_q2[CHNL_BW_MAX];
+ s8 ant_factor_q2[MAX_ANTENNAS];
+};
+
+struct cl_tx_power_info {
+ s8 power;
+ s8 offset;
+ s8 temperature;
+};
+
+struct cl_power_truncate {
+ u8 he[CHNL_BW_MAX][WRS_MCS_MAX_HE][PWR_TBL_HE_BF_SIZE];
+ u8 ht_vht[CHNL_BW_MAX][WRS_MCS_MAX_VHT][PWR_TBL_VHT_BF_SIZE];
+ u8 ofdm[WRS_MCS_MAX_OFDM];
+ u8 cck[WRS_MCS_MAX_CCK];
+};
+
+int cl_power_table_alloc(struct cl_hw *cl_hw);
+void cl_power_table_free(struct cl_hw *cl_hw);
+u8 cl_power_tx_ant(struct cl_hw *cl_hw, enum cl_wrs_mode mode);
+s32 cl_power_antenna_gain_q8(struct cl_hw *cl_hw);
+s32 cl_power_antenna_gain_q1(struct cl_hw *cl_hw);
+s32 cl_power_array_gain_q8(struct cl_hw *cl_hw, u8 tx_ant);
+s8 cl_power_array_gain_q2(struct cl_hw *cl_hw, u8 tx_ant);
+s32 cl_power_array_gain_q1(struct cl_hw *cl_hw, u8 tx_ant);
+s32 cl_power_bf_gain_q1(struct cl_hw *cl_hw, u8 tx_ant, u8 nss);
+s32 cl_power_min_ant_q1(struct cl_hw *cl_hw);
+s8 cl_power_bw_factor_q2(struct cl_hw *cl_hw, u8 bw);
+s32 cl_power_average_calib_q1(struct cl_hw *cl_hw, u8 ant_num);
+s8 cl_power_offset_q1(struct cl_hw *cl_hw, u8 mode, u8 bw, u8 mcs);
+s8 cl_power_offset_check_margin(struct cl_hw *cl_hw, u8 bw, u8 ant_idx, s8 offset_q2);
+void cl_power_tables_update(struct cl_hw *cl_hw, struct cl_pwr_tables *pwr_tables);
+s32 cl_power_get_max(struct cl_hw *cl_hw);
+
+#endif /* CL_POWER_H */
--
2.36.1
