> Le 16 avr. 2022 à 20:39, Felix Fietkau <nbd@xxxxxxxx> a écrit : > The patch looks wrong to me. I'm pretty sure that AR_CH0_TOP2 is the correct register, the definition has an explicit check for 9561 as well. > I believe this patch works by accident because it avoids writing a wrong value to that register. > The value written to that register is wrong, because while the mask definition AR_CH0_TOP2_XPABIASLVL uses a different value for 9561, the shift definition AR_CH0_TOP2_XPABIASLVL_S is hardcoded to 12, which is wrong for 9561. > Please try adjusting it to this: > #define AR_CH0_TOP2_XPABIASLVL_S (AR_SREV_9561(ah) ? 9 : 12) This works, thanks. I’ll submit a v2 now. Thibaut
