Anilkumar Kolli <akolli@xxxxxxxxxxxxxx> writes:
> Host DDR memory (contiguous 45 MB in mode-0 or 15 MB in mode-2)
> is reserved through DT entries for firmware usage. Send the base
> address from DT entries.
> If DT entry is available, PCI device will work with
> fixed_mem_region else host allocates multiple segments.
>
> IPQ8074 on HK10 board supports multiple PCI devices.
> IPQ8074 + QCN9074 is tested with this patch.
>
> Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.4.0.1-01838-QCAHKSWPL_SILICONZ-1
>
> Signed-off-by: Anilkumar Kolli <akolli@xxxxxxxxxxxxxx>
Not sure how I missed these in the last round:
> +static bool ath11k_mhi_read_addr_from_dt(struct mhi_controller *mhi_ctrl)
static int ....
> +{
> + struct device_node *np;
> + u32 reg[4];
> + dma_addr_t start;
> +
> + np = of_find_node_by_type(NULL, "memory");
> + if (!np)
> + return false;
> +
> + if (of_property_read_u32_array(np, "reg", reg, 4))
> + return false;
ret = of_property_read_u32_array(np, "reg", reg, 4);
if (ret)
return ret;
> + start = reg[0] + reg[1];
> + mhi_ctrl->iova_start = start + 0x1000000;
> + mhi_ctrl->iova_stop = start + reg[2] + reg[3];
> +
> + return true;
return 0;
> +}
> +
> int ath11k_mhi_register(struct ath11k_pci *ab_pci)
> {
> struct ath11k_base *ab = ab_pci->ab;
> @@ -339,8 +360,14 @@ int ath11k_mhi_register(struct ath11k_pci *ab_pci)
> return ret;
> }
>
> - mhi_ctrl->iova_start = 0;
> - mhi_ctrl->iova_stop = 0xffffffff;
> + if ((test_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags))) {
> + if (!ath11k_mhi_read_addr_from_dt(mhi_ctrl))
> + return -ENODATA;
ret = ath11k_mhi_read_addr_from_dt(mhi_ctrl);
if (ret)
return ret;
> @@ -1245,6 +1246,13 @@ static int ath11k_pci_probe(struct pci_dev *pdev,
> pci_set_drvdata(pdev, ab);
> spin_lock_init(&ab_pci->window_lock);
>
> + /* Set fixed_mem_region to true for platforms support reserved memory
> + * from DT. If memory is reserved from DT for FW, ath11k driver need not
> + * allocate memory.
> + */
> + if (!of_property_read_u32(ab->dev->of_node, "memory-region", &addr))
> + set_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags);
ret = of_property_read_u32(ab->dev->of_node, "memory-region", &addr);
if (!ret)
set_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags);
> static int ath11k_qmi_assign_target_mem_chunk(struct ath11k_base *ab)
> {
> + struct device *dev = ab->dev;
> + struct device_node *hremote_node = NULL;
> + phandle hremote_phandle;
> + dma_addr_t start;
> + u32 reg[4], size, host_ddr_sz;
> int i, idx;
>
> for (i = 0, idx = 0; i < ab->qmi.mem_seg_count; i++) {
> switch (ab->qmi.target_mem[i].type) {
> + case HOST_DDR_REGION_TYPE:
> + if (of_property_read_u32(dev->of_node, "memory-region",
> + &hremote_phandle)) {
> + ath11k_dbg(ab, ATH11K_DBG_QMI,
> + "qmi fail to get hremote phandle\n");
> + return 0;
> + }
> +
> + hremote_node = of_find_node_by_phandle(hremote_phandle);
> + if (!hremote_node) {
> + ath11k_dbg(ab, ATH11K_DBG_QMI,
> + "qmi fail to get hremote_node\n");
> + return 0;
> + }
> +
> + if (of_property_read_u32_array(hremote_node, "reg", reg, 4)) {
> + ath11k_dbg(ab, ATH11K_DBG_QMI,
> + "qmi fail to get reg from hremote\n");
> + return 0;
> + }
ret = of_property_read_u32_array(hremote_node, "reg", reg, 4);
if (ret) {
ath11k_dbg(ab, ATH11K_DBG_QMI,
"qmi fail to get reg from hremote\n");
return 0;
}
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