On Tue, Nov 09, 2021 at 10:33:58AM +0530, Anilkumar Kolli wrote: > On 2021-11-02 02:05, Rob Herring wrote: > > On Mon, Oct 25, 2021 at 08:57:27PM +0530, Anilkumar Kolli wrote: > > > Ath11k driver supports PCI devices such as QCN9074/QCA6390. > > > Ath11k firmware uses host DDR memory, DT entry is used to reserve > > > these host DDR memory regions, send these memory base > > > addresses using DT entries. > > > > > > Signed-off-by: Anilkumar Kolli <akolli@xxxxxxxxxxxxxx> > > > --- > > > .../bindings/net/wireless/qcom,ath11k.yaml | 38 > > > ++++++++++++++++++++++ > > > 1 file changed, 38 insertions(+) > > > > > > diff --git > > > a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml > > > b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml > > > index 5ac9616c9239..c7e6612e949c 100644 > > > --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml > > > +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml > > > @@ -19,6 +19,10 @@ description: | > > > These devices use HOST DDR memory, HOST DDR memory can be reserved > > > and send to ath11k driver from DT. > > > > > > + ATH11K supports PCI devices like QCA6390,QCN9074. > > > + These devices use host DDR memory, host DDR memory can be reserved > > > + and send to ath11k driver from DT. > > > + > > > properties: > > > compatible: > > > enum: > > > @@ -177,6 +181,29 @@ properties: > > > description: > > > HOST DDR end address. > > > > > > + qcom,base-addr: > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > + description: > > > + Host DDR base address for firmware. QCN9074 firmware uses 45 > > > MB of host > > > + DDR memory in mode-0 and 15 MB of host DDR memory in mode-2. > > > + > > > + qcom,caldb-addr: > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > + description: > > > + Host DDR address to store CALDB. CALDB is calibration data base > > > + for WLAN channel and tx power. > > > + > > > > Use /reserved-memory entries for these. > > > > Sure. > > > > + qcom,start-addr: > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > + description: > > > + Host DDR start address. For example on x86 it is 0x0, > > > + on IPQ8074 it is 0x41000000. > > > + > > > + qcom,end-addr: > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > + description: > > > + Host DDR end address. > > > > Nak. I don't know what you are doing with these 2, but it's wrong. > > > > The DDR start address and end address are sent to MHI control bus, > For x86 platform code snip in ath11k/mhi.c > > mhi_ctrl->iova_start = 0; > mhi_ctrl->iova_stop = 0xffffffff; > > Similarly for ARM platfroms, send DDR addresses from DT entry. > You can use the reserved memory node for ddr address also. In the ath11k driver, use devicetree APIs for fetching the start and end addresses. Thanks, Mani > Thanks > Anil
