2008/9/28 Bob Copeland <me@xxxxxxxxxxxxxxx>:
> According to the newly-released Atheros HAL code, asserting the
> TSF reset bit will toggle a hardware internal state, resulting in a
> spurious reset on the next chip reset. Whenever we force a TSF bit,
> write the bit twice to clear the internal signal.
>
> Signed-off-by: Bob Copeland <me@xxxxxxxxxxxxxxx>
> ---
>
> This was the only major difference I found between code we're currently
> using in pcu.c and its equivalents in the HAL. See comment in
> ar5212ResetTsf. This is only compile-tested.
>
> (There are other differences but they are in the key setup code or
> beacon setup code that we are not using right now.)
>
> drivers/net/wireless/ath5k/pcu.c | 14 +++++++++++++-
> 1 files changed, 13 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/net/wireless/ath5k/pcu.c b/drivers/net/wireless/ath5k/pcu.c
> index c77cee2..c8f9170 100644
> --- a/drivers/net/wireless/ath5k/pcu.c
> +++ b/drivers/net/wireless/ath5k/pcu.c
> @@ -633,8 +633,20 @@ u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
> */
> void ath5k_hw_reset_tsf(struct ath5k_hw *ah)
> {
> + u32 val;
> +
> ATH5K_TRACE(ah->ah_sc);
> - AR5K_REG_ENABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_RESET_TSF);
> +
> + val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF;
> +
> + /*
> + * Each write to the RESET_TSF bit toggles a hardware internal
> + * signal to reset TSF, but if left high it will cause a TSF reset
> + * on the next chip reset as well. Thus we always write the value
> + * twice to clear the signal.
> + */
> + ath5k_hw_reg_write(ah, val, AR5K_BEACON);
> + ath5k_hw_reg_write(ah, val, AR5K_BEACON);
> }
>
> /*
> --
> 1.5.4.2.182.gb3092
>
> --
> Bob Copeland %% www.bobcopeland.com
>
> _______________________________________________
> ath5k-devel mailing list
> ath5k-devel@xxxxxxxxxxxxxxx
> https://lists.ath5k.org/mailman/listinfo/ath5k-devel
>
Acked-by: Nick Kossifidis <mickflemm@xxxxxxxxx>
--
GPG ID: 0xD21DB2DB
As you read this post global entropy rises. Have Fun ;-)
Nick
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