From: Viktor Barna <viktor.barna@xxxxxxxxxx>
(Part of the split. Please, take a look at the cover letter for more
details).
Signed-off-by: Viktor Barna <viktor.barna@xxxxxxxxxx>
---
.../net/wireless/celeno/cl8k/reg/reg_ricu.h | 1326 +++++++++++++++++
1 file changed, 1326 insertions(+)
create mode 100644 drivers/net/wireless/celeno/cl8k/reg/reg_ricu.h
diff --git a/drivers/net/wireless/celeno/cl8k/reg/reg_ricu.h b/drivers/net/wireless/celeno/cl8k/reg/reg_ricu.h
new file mode 100644
index 000000000000..00e4759db751
--- /dev/null
+++ b/drivers/net/wireless/celeno/cl8k/reg/reg_ricu.h
@@ -0,0 +1,1326 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright(c) 2019-2021, Celeno Communications Ltd. */
+
+#ifndef CL_REG_RICU_H
+#define CL_REG_RICU_H
+
+#include "reg/reg_access.h"
+#include "chip.h"
+
+/*
+ * @brief STATIC_CONF_0 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 30 ARB_ONESHOT_BYPASS 1
+ * 28 BTC_SEL 0
+ * 27 CLK_SAVE_MODE 0
+ * 26 RF_RST_N_DEFAULT 0
+ * 25 RF_RST_N_REQ 0
+ * 24 FORCE_RSSI_ON 0
+ * 23:20 RSSI_M 0x2
+ * 19:16 RSSI_N 0x6
+ * 03:00 CDB_MODE_MAJ 0x0
+ * </pre>
+ */
+#define RICU_STATIC_CONF_0_ADDR (REG_RICU_BASE_ADDR + 0x00000004)
+#define RICU_STATIC_CONF_0_OFFSET 0x00000004
+#define RICU_STATIC_CONF_0_INDEX 0x00000001
+#define RICU_STATIC_CONF_0_RESET 0x40260000
+
+static inline void ricu_static_conf_0_btc_sel_setf(struct cl_chip *chip, u8 btcsel)
+{
+ ASSERT_ERR_CHIP((((u32)btcsel << 28) & ~((u32)0x10000000)) == 0);
+ cl_reg_write_chip(chip, RICU_STATIC_CONF_0_ADDR, (cl_reg_read_chip(chip, RICU_STATIC_CONF_0_ADDR) & ~((u32)0x10000000)) | ((u32)btcsel << 28));
+}
+
+static inline void ricu_static_conf_0_rf_rst_n_req_setf(struct cl_chip *chip, u8 rfrstnreq)
+{
+ ASSERT_ERR_CHIP((((u32)rfrstnreq << 25) & ~((u32)0x02000000)) == 0);
+ cl_reg_write_chip(chip, RICU_STATIC_CONF_0_ADDR, (cl_reg_read_chip(chip, RICU_STATIC_CONF_0_ADDR) & ~((u32)0x02000000)) | ((u32)rfrstnreq << 25));
+}
+
+static inline u8 ricu_static_conf_0_cdb_mode_maj_getf(struct cl_chip *chip)
+{
+ u32 local_val = cl_reg_read_chip(chip, RICU_STATIC_CONF_0_ADDR);
+
+ return ((local_val & ((u32)0x0000000F)) >> 0);
+}
+
+static inline void ricu_static_conf_0_cdb_mode_maj_setf(struct cl_chip *chip, u8 cdbmodemaj)
+{
+ ASSERT_ERR_CHIP((((u32)cdbmodemaj << 0) & ~((u32)0x0000000F)) == 0);
+ cl_reg_write_chip(chip, RICU_STATIC_CONF_0_ADDR, (cl_reg_read_chip(chip, RICU_STATIC_CONF_0_ADDR) & ~((u32)0x0000000F)) | ((u32)cdbmodemaj << 0));
+}
+
+/*
+ * @brief AFE_CTL_0 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31 PBIAS_CTRL_EN_LC 0
+ * 30 PBIAS_CTRL_EN 0
+ * 29 LRD_EN_LC 0
+ * 28 LRD_EN 0
+ * 27 LOCK_EN_LC 0
+ * 26 LOCK_EN 1
+ * 25 EN_GPADC_CLK 0
+ * 24 EN_GPADC 0
+ * 23 FEED_EN_LC 0
+ * 22 FEED_EN 0
+ * 21 EN_CS 1
+ * 20 EN_CML_GEN 1
+ * 18 EN_AFE_LDO 1
+ * 17 EN_ADC_CLK 1
+ * 15 AFC_ENB_LC 0
+ * 14 AFC_ENB 0
+ * 13 CP_MODE_LC 1
+ * 12 BYPASS_LC 0
+ * 11 BYPASS 0
+ * 10 AFCINIT_SEL_LC 1
+ * 09 AFCINIT_SEL 1
+ * 08 EN_CLK_MON 0
+ * 07 EN_DAC_CLK 1
+ * 06 EN_CDB_DAC_CLK 0
+ * 05 EN_CDB_ADC_CLK 0
+ * 03 EN_CDB_GEN 0
+ * 02 DACCLK_PHASESEL 0
+ * 01 ADCCLK_PHASESEL 0
+ * 00 CDB_CLK_RESETB 0
+ * </pre>
+ */
+#define RICU_AFE_CTL_0_ADDR (REG_RICU_BASE_ADDR + 0x00000010)
+#define RICU_AFE_CTL_0_OFFSET 0x00000010
+#define RICU_AFE_CTL_0_INDEX 0x00000004
+#define RICU_AFE_CTL_0_RESET 0x04362680
+
+static inline u32 ricu_afe_ctl_0_get(struct cl_chip *chip)
+{
+ return cl_reg_read_chip(chip, RICU_AFE_CTL_0_ADDR);
+}
+
+static inline void ricu_afe_ctl_0_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, RICU_AFE_CTL_0_ADDR, value);
+}
+
+/* Field definitions */
+#define RICU_AFE_CTL_0_PBIAS_CTRL_EN_LC_BIT ((u32)0x80000000)
+#define RICU_AFE_CTL_0_PBIAS_CTRL_EN_LC_POS 31
+#define RICU_AFE_CTL_0_PBIAS_CTRL_EN_BIT ((u32)0x40000000)
+#define RICU_AFE_CTL_0_PBIAS_CTRL_EN_POS 30
+#define RICU_AFE_CTL_0_LRD_EN_LC_BIT ((u32)0x20000000)
+#define RICU_AFE_CTL_0_LRD_EN_LC_POS 29
+#define RICU_AFE_CTL_0_LRD_EN_BIT ((u32)0x10000000)
+#define RICU_AFE_CTL_0_LRD_EN_POS 28
+#define RICU_AFE_CTL_0_LOCK_EN_LC_BIT ((u32)0x08000000)
+#define RICU_AFE_CTL_0_LOCK_EN_LC_POS 27
+#define RICU_AFE_CTL_0_LOCK_EN_BIT ((u32)0x04000000)
+#define RICU_AFE_CTL_0_LOCK_EN_POS 26
+#define RICU_AFE_CTL_0_EN_GPADC_CLK_BIT ((u32)0x02000000)
+#define RICU_AFE_CTL_0_EN_GPADC_CLK_POS 25
+#define RICU_AFE_CTL_0_EN_GPADC_BIT ((u32)0x01000000)
+#define RICU_AFE_CTL_0_EN_GPADC_POS 24
+#define RICU_AFE_CTL_0_FEED_EN_LC_BIT ((u32)0x00800000)
+#define RICU_AFE_CTL_0_FEED_EN_LC_POS 23
+#define RICU_AFE_CTL_0_FEED_EN_BIT ((u32)0x00400000)
+#define RICU_AFE_CTL_0_FEED_EN_POS 22
+#define RICU_AFE_CTL_0_EN_CS_BIT ((u32)0x00200000)
+#define RICU_AFE_CTL_0_EN_CS_POS 21
+#define RICU_AFE_CTL_0_EN_CML_GEN_BIT ((u32)0x00100000)
+#define RICU_AFE_CTL_0_EN_CML_GEN_POS 20
+#define RICU_AFE_CTL_0_EN_AFE_LDO_BIT ((u32)0x00040000)
+#define RICU_AFE_CTL_0_EN_AFE_LDO_POS 18
+#define RICU_AFE_CTL_0_EN_ADC_CLK_BIT ((u32)0x00020000)
+#define RICU_AFE_CTL_0_EN_ADC_CLK_POS 17
+#define RICU_AFE_CTL_0_AFC_ENB_LC_BIT ((u32)0x00008000)
+#define RICU_AFE_CTL_0_AFC_ENB_LC_POS 15
+#define RICU_AFE_CTL_0_AFC_ENB_BIT ((u32)0x00004000)
+#define RICU_AFE_CTL_0_AFC_ENB_POS 14
+#define RICU_AFE_CTL_0_CP_MODE_LC_BIT ((u32)0x00002000)
+#define RICU_AFE_CTL_0_CP_MODE_LC_POS 13
+#define RICU_AFE_CTL_0_BYPASS_LC_BIT ((u32)0x00001000)
+#define RICU_AFE_CTL_0_BYPASS_LC_POS 12
+#define RICU_AFE_CTL_0_BYPASS_BIT ((u32)0x00000800)
+#define RICU_AFE_CTL_0_BYPASS_POS 11
+#define RICU_AFE_CTL_0_AFCINIT_SEL_LC_BIT ((u32)0x00000400)
+#define RICU_AFE_CTL_0_AFCINIT_SEL_LC_POS 10
+#define RICU_AFE_CTL_0_AFCINIT_SEL_BIT ((u32)0x00000200)
+#define RICU_AFE_CTL_0_AFCINIT_SEL_POS 9
+#define RICU_AFE_CTL_0_EN_CLK_MON_BIT ((u32)0x00000100)
+#define RICU_AFE_CTL_0_EN_CLK_MON_POS 8
+#define RICU_AFE_CTL_0_EN_DAC_CLK_BIT ((u32)0x00000080)
+#define RICU_AFE_CTL_0_EN_DAC_CLK_POS 7
+#define RICU_AFE_CTL_0_EN_CDB_DAC_CLK_BIT ((u32)0x00000040)
+#define RICU_AFE_CTL_0_EN_CDB_DAC_CLK_POS 6
+#define RICU_AFE_CTL_0_EN_CDB_ADC_CLK_BIT ((u32)0x00000020)
+#define RICU_AFE_CTL_0_EN_CDB_ADC_CLK_POS 5
+#define RICU_AFE_CTL_0_EN_CDB_GEN_BIT ((u32)0x00000008)
+#define RICU_AFE_CTL_0_EN_CDB_GEN_POS 3
+#define RICU_AFE_CTL_0_DACCLK_PHASESEL_BIT ((u32)0x00000004)
+#define RICU_AFE_CTL_0_DACCLK_PHASESEL_POS 2
+#define RICU_AFE_CTL_0_ADCCLK_PHASESEL_BIT ((u32)0x00000002)
+#define RICU_AFE_CTL_0_ADCCLK_PHASESEL_POS 1
+#define RICU_AFE_CTL_0_CDB_CLK_RESETB_BIT ((u32)0x00000001)
+#define RICU_AFE_CTL_0_CDB_CLK_RESETB_POS 0
+
+static inline void ricu_afe_ctl_0_pbias_ctrl_en_lc_setf(struct cl_chip *chip, u8 pbiasctrlenlc)
+{
+ cl_reg_write_chip(chip, RICU_AFE_CTL_0_ADDR, (cl_reg_read_chip(chip, RICU_AFE_CTL_0_ADDR) & ~((u32)0x80000000)) | ((u32)pbiasctrlenlc << 31));
+}
+
+static inline void ricu_afe_ctl_0_cdb_clk_resetb_setf(struct cl_chip *chip, u8 cdbclkresetb)
+{
+ ASSERT_ERR_CHIP((((u32)cdbclkresetb << 0) & ~((u32)0x00000001)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTL_0_ADDR, (cl_reg_read_chip(chip, RICU_AFE_CTL_0_ADDR) & ~((u32)0x00000001)) | ((u32)cdbclkresetb << 0));
+}
+
+/*
+ * @brief AFE_CTL_1 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 14 VCO_BOOST 0
+ * 13 SYS_ADCCLK_SEL 0
+ * 12 SOC_PHASE_SEL 1
+ * 11 SOC_CLK_SEL 1
+ * 10 RESETB_LC 0
+ * 09 RESETB 1
+ * 08 PBIAS_CTRL_LC 0
+ * 07 PBIAS_CTRL 0
+ * 06 GP_CLK_PHASESEL 0
+ * 05 FSEL_LC 0
+ * 04 FSEL 0
+ * 03 FOUT_MASK_LC 0
+ * 02 FOUT_MASK 0
+ * 01 EXTCLK_SEL 0
+ * 00 EN_PLL_LDO 0
+ * </pre>
+ */
+#define RICU_AFE_CTL_1_ADDR (REG_RICU_BASE_ADDR + 0x00000014)
+#define RICU_AFE_CTL_1_OFFSET 0x00000014
+#define RICU_AFE_CTL_1_INDEX 0x00000005
+#define RICU_AFE_CTL_1_RESET 0x00001A00
+
+static inline void ricu_afe_ctl_1_resetb_lc_setf(struct cl_chip *chip, u8 resetblc)
+{
+ ASSERT_ERR_CHIP((((u32)resetblc << 10) & ~((u32)0x00000400)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTL_1_ADDR, (cl_reg_read_chip(chip, RICU_AFE_CTL_1_ADDR) & ~((u32)0x00000400)) | ((u32)resetblc << 10));
+}
+
+static inline void ricu_afe_ctl_1_en_pll_ldo_setf(struct cl_chip *chip, u8 enpllldo)
+{
+ ASSERT_ERR_CHIP((((u32)enpllldo << 0) & ~((u32)0x00000001)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTL_1_ADDR, (cl_reg_read_chip(chip, RICU_AFE_CTL_1_ADDR) & ~((u32)0x00000001)) | ((u32)enpllldo << 0));
+}
+
+/*
+ * @brief AFE_CTL_2 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 23:22 LOCK_CON_REV_LC 0x0
+ * 21:20 LOCK_CON_REV 0x0
+ * 19:18 LOCK_CON_OUT_LC 0x3
+ * 17:16 LOCK_CON_OUT 0x3
+ * 15:14 LOCK_CON_IN_LC 0x3
+ * 13:12 LOCK_CON_IN 0x3
+ * 11:10 LOCK_CON_DLY_LC 0x3
+ * 09:08 LOCK_CON_DLY 0x3
+ * 07:06 ICP 0x1
+ * 03:02 CTRL_IB 0x2
+ * 01:00 CLK_MON_SEL 0x0
+ * </pre>
+ */
+#define RICU_AFE_CTL_2_ADDR (REG_RICU_BASE_ADDR + 0x00000018)
+#define RICU_AFE_CTL_2_OFFSET 0x00000018
+#define RICU_AFE_CTL_2_INDEX 0x00000006
+#define RICU_AFE_CTL_2_RESET 0x000FFF48
+
+static inline void ricu_afe_ctl_2_lock_con_rev_lc_setf(struct cl_chip *chip, u8 lockconrevlc)
+{
+ ASSERT_ERR_CHIP((((u32)lockconrevlc << 22) & ~((u32)0x00C00000)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTL_2_ADDR, (cl_reg_read_chip(chip, RICU_AFE_CTL_2_ADDR) & ~((u32)0x00C00000)) | ((u32)lockconrevlc << 22));
+}
+
+/*
+ * @brief AFE_CTL_3 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31:28 RSEL 0x0
+ * 27:24 I_CSEL_LC 0xc
+ * 23:20 GM_LC 0xf
+ * 19:16 CSEL_LC 0x3
+ * 15:12 CML_SEL 0x9
+ * 11:09 S_LC 0x0
+ * 08:06 S 0x0
+ * 05:03 LBW_LC 0x7
+ * 02:00 ICP_LC 0x7
+ * </pre>
+ */
+#define RICU_AFE_CTL_3_ADDR (REG_RICU_BASE_ADDR + 0x0000001C)
+#define RICU_AFE_CTL_3_OFFSET 0x0000001C
+#define RICU_AFE_CTL_3_INDEX 0x00000007
+#define RICU_AFE_CTL_3_RESET 0x0CF3903F
+
+static inline void ricu_afe_ctl_3_cml_sel_setf(struct cl_chip *chip, u8 cmlsel)
+{
+ ASSERT_ERR_CHIP((((u32)cmlsel << 12) & ~((u32)0x0000F000)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTL_3_ADDR, (cl_reg_read_chip(chip, RICU_AFE_CTL_3_ADDR) & ~((u32)0x0000F000)) | ((u32)cmlsel << 12));
+}
+
+/*
+ * @brief AFE_CTL_5 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 23:18 MAIN_SEL_7_2 0x0
+ * 17:12 P_LC 0x1
+ * 11:06 P 0xA
+ * 05:00 CAP_BIAS_CODE_LC 0x4
+ * </pre>
+ */
+#define RICU_AFE_CTL_5_ADDR (REG_RICU_BASE_ADDR + 0x00000024)
+#define RICU_AFE_CTL_5_OFFSET 0x00000024
+#define RICU_AFE_CTL_5_INDEX 0x00000009
+#define RICU_AFE_CTL_5_RESET 0x00001284
+
+static inline void ricu_afe_ctl_5_main_sel_7_2_setf(struct cl_chip *chip, u8 mainsel72)
+{
+ ASSERT_ERR_CHIP((((u32)mainsel72 << 18) & ~((u32)0x00FC0000)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTL_5_ADDR, (cl_reg_read_chip(chip, RICU_AFE_CTL_5_ADDR) & ~((u32)0x00FC0000)) | ((u32)mainsel72 << 18));
+}
+
+/*
+ * @brief AFE_CTL_8 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31 EN_REF7 0
+ * 30 EN_REF6 0
+ * 29 EN_REF5 0
+ * 28 EN_REF4 0
+ * 27 EN_REF3 0
+ * 26 EN_REF2 0
+ * 25 EN_REF1 0
+ * 24 EN_REF0 0
+ * 23 EN_EXT_LOAD7 0
+ * 22 EN_EXT_LOAD6 0
+ * 21 EN_EXT_LOAD5 0
+ * 20 EN_EXT_LOAD4 0
+ * 19 EN_EXT_LOAD3 0
+ * 18 EN_EXT_LOAD2 0
+ * 17 EN_EXT_LOAD1 0
+ * 16 EN_EXT_LOAD0 0
+ * 15 CH_CML_SEL7 0
+ * 14 CH_CML_SEL6 0
+ * 13 CH_CML_SEL5 0
+ * 12 CH_CML_SEL4 0
+ * 11 CH_CML_SEL3 0
+ * 10 CH_CML_SEL2 0
+ * 09 CH_CML_SEL1 0
+ * 08 CH_CML_SEL0 0
+ * 07 EN_BGR7 0
+ * 06 EN_BGR6 0
+ * 05 EN_BGR5 0
+ * 04 EN_BGR4 0
+ * 03 EN_BGR3 0
+ * 02 EN_BGR2 0
+ * 01 EN_BGR1 0
+ * 00 EN_BGR0 0
+ * </pre>
+ */
+#define RICU_AFE_CTL_8_ADDR (REG_RICU_BASE_ADDR + 0x00000030)
+#define RICU_AFE_CTL_8_OFFSET 0x00000030
+#define RICU_AFE_CTL_8_INDEX 0x0000000C
+#define RICU_AFE_CTL_8_RESET 0x00000000
+
+static inline u32 ricu_afe_ctl_8_get(struct cl_chip *chip)
+{
+ return cl_reg_read_chip(chip, RICU_AFE_CTL_8_ADDR);
+}
+
+static inline void ricu_afe_ctl_8_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, RICU_AFE_CTL_8_ADDR, value);
+}
+
+/* Field definitions */
+#define RICU_AFE_CTL_8_EN_REF_7_BIT ((u32)0x80000000)
+#define RICU_AFE_CTL_8_EN_REF_7_POS 31
+#define RICU_AFE_CTL_8_EN_REF_6_BIT ((u32)0x40000000)
+#define RICU_AFE_CTL_8_EN_REF_6_POS 30
+#define RICU_AFE_CTL_8_EN_REF_5_BIT ((u32)0x20000000)
+#define RICU_AFE_CTL_8_EN_REF_5_POS 29
+#define RICU_AFE_CTL_8_EN_REF_4_BIT ((u32)0x10000000)
+#define RICU_AFE_CTL_8_EN_REF_4_POS 28
+#define RICU_AFE_CTL_8_EN_REF_3_BIT ((u32)0x08000000)
+#define RICU_AFE_CTL_8_EN_REF_3_POS 27
+#define RICU_AFE_CTL_8_EN_REF_2_BIT ((u32)0x04000000)
+#define RICU_AFE_CTL_8_EN_REF_2_POS 26
+#define RICU_AFE_CTL_8_EN_REF_1_BIT ((u32)0x02000000)
+#define RICU_AFE_CTL_8_EN_REF_1_POS 25
+#define RICU_AFE_CTL_8_EN_REF_0_BIT ((u32)0x01000000)
+#define RICU_AFE_CTL_8_EN_REF_0_POS 24
+#define RICU_AFE_CTL_8_EN_EXT_LOAD_7_BIT ((u32)0x00800000)
+#define RICU_AFE_CTL_8_EN_EXT_LOAD_7_POS 23
+#define RICU_AFE_CTL_8_EN_EXT_LOAD_6_BIT ((u32)0x00400000)
+#define RICU_AFE_CTL_8_EN_EXT_LOAD_6_POS 22
+#define RICU_AFE_CTL_8_EN_EXT_LOAD_5_BIT ((u32)0x00200000)
+#define RICU_AFE_CTL_8_EN_EXT_LOAD_5_POS 21
+#define RICU_AFE_CTL_8_EN_EXT_LOAD_4_BIT ((u32)0x00100000)
+#define RICU_AFE_CTL_8_EN_EXT_LOAD_4_POS 20
+#define RICU_AFE_CTL_8_EN_EXT_LOAD_3_BIT ((u32)0x00080000)
+#define RICU_AFE_CTL_8_EN_EXT_LOAD_3_POS 19
+#define RICU_AFE_CTL_8_EN_EXT_LOAD_2_BIT ((u32)0x00040000)
+#define RICU_AFE_CTL_8_EN_EXT_LOAD_2_POS 18
+#define RICU_AFE_CTL_8_EN_EXT_LOAD_1_BIT ((u32)0x00020000)
+#define RICU_AFE_CTL_8_EN_EXT_LOAD_1_POS 17
+#define RICU_AFE_CTL_8_EN_EXT_LOAD_0_BIT ((u32)0x00010000)
+#define RICU_AFE_CTL_8_EN_EXT_LOAD_0_POS 16
+#define RICU_AFE_CTL_8_CH_CML_SEL_7_BIT ((u32)0x00008000)
+#define RICU_AFE_CTL_8_CH_CML_SEL_7_POS 15
+#define RICU_AFE_CTL_8_CH_CML_SEL_6_BIT ((u32)0x00004000)
+#define RICU_AFE_CTL_8_CH_CML_SEL_6_POS 14
+#define RICU_AFE_CTL_8_CH_CML_SEL_5_BIT ((u32)0x00002000)
+#define RICU_AFE_CTL_8_CH_CML_SEL_5_POS 13
+#define RICU_AFE_CTL_8_CH_CML_SEL_4_BIT ((u32)0x00001000)
+#define RICU_AFE_CTL_8_CH_CML_SEL_4_POS 12
+#define RICU_AFE_CTL_8_CH_CML_SEL_3_BIT ((u32)0x00000800)
+#define RICU_AFE_CTL_8_CH_CML_SEL_3_POS 11
+#define RICU_AFE_CTL_8_CH_CML_SEL_2_BIT ((u32)0x00000400)
+#define RICU_AFE_CTL_8_CH_CML_SEL_2_POS 10
+#define RICU_AFE_CTL_8_CH_CML_SEL_1_BIT ((u32)0x00000200)
+#define RICU_AFE_CTL_8_CH_CML_SEL_1_POS 9
+#define RICU_AFE_CTL_8_CH_CML_SEL_0_BIT ((u32)0x00000100)
+#define RICU_AFE_CTL_8_CH_CML_SEL_0_POS 8
+#define RICU_AFE_CTL_8_EN_BGR_7_BIT ((u32)0x00000080)
+#define RICU_AFE_CTL_8_EN_BGR_7_POS 7
+#define RICU_AFE_CTL_8_EN_BGR_6_BIT ((u32)0x00000040)
+#define RICU_AFE_CTL_8_EN_BGR_6_POS 6
+#define RICU_AFE_CTL_8_EN_BGR_5_BIT ((u32)0x00000020)
+#define RICU_AFE_CTL_8_EN_BGR_5_POS 5
+#define RICU_AFE_CTL_8_EN_BGR_4_BIT ((u32)0x00000010)
+#define RICU_AFE_CTL_8_EN_BGR_4_POS 4
+#define RICU_AFE_CTL_8_EN_BGR_3_BIT ((u32)0x00000008)
+#define RICU_AFE_CTL_8_EN_BGR_3_POS 3
+#define RICU_AFE_CTL_8_EN_BGR_2_BIT ((u32)0x00000004)
+#define RICU_AFE_CTL_8_EN_BGR_2_POS 2
+#define RICU_AFE_CTL_8_EN_BGR_1_BIT ((u32)0x00000002)
+#define RICU_AFE_CTL_8_EN_BGR_1_POS 1
+#define RICU_AFE_CTL_8_EN_BGR_0_BIT ((u32)0x00000001)
+#define RICU_AFE_CTL_8_EN_BGR_0_POS 0
+
+/*
+ * @brief AFE_CTL_9 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31 EN_SIN2_BIAS7 1
+ * 30 EN_SIN2_BIAS6 1
+ * 29 EN_SIN2_BIAS5 1
+ * 28 EN_SIN2_BIAS4 1
+ * 27 EN_SIN2_BIAS3 1
+ * 26 EN_SIN2_BIAS2 1
+ * 25 EN_SIN2_BIAS1 1
+ * 24 EN_SIN2_BIAS0 1
+ * 23 EN_DAC_REF7 0
+ * 22 EN_DAC_REF6 0
+ * 21 EN_DAC_REF5 0
+ * 20 EN_DAC_REF4 0
+ * 19 EN_DAC_REF3 0
+ * 18 EN_DAC_REF2 0
+ * 17 EN_DAC_REF1 0
+ * 16 EN_DAC_REF0 0
+ * </pre>
+ */
+#define RICU_AFE_CTL_9_ADDR (REG_RICU_BASE_ADDR + 0x00000034)
+#define RICU_AFE_CTL_9_OFFSET 0x00000034
+#define RICU_AFE_CTL_9_INDEX 0x0000000D
+#define RICU_AFE_CTL_9_RESET 0xFF000000
+
+static inline u32 ricu_afe_ctl_9_get(struct cl_chip *chip)
+{
+ return cl_reg_read_chip(chip, RICU_AFE_CTL_9_ADDR);
+}
+
+static inline void ricu_afe_ctl_9_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, RICU_AFE_CTL_9_ADDR, value);
+}
+
+/* Field definitions */
+#define RICU_AFE_CTL_9_EN_SIN_2_BIAS_7_BIT ((u32)0x80000000)
+#define RICU_AFE_CTL_9_EN_SIN_2_BIAS_7_POS 31
+#define RICU_AFE_CTL_9_EN_SIN_2_BIAS_6_BIT ((u32)0x40000000)
+#define RICU_AFE_CTL_9_EN_SIN_2_BIAS_6_POS 30
+#define RICU_AFE_CTL_9_EN_SIN_2_BIAS_5_BIT ((u32)0x20000000)
+#define RICU_AFE_CTL_9_EN_SIN_2_BIAS_5_POS 29
+#define RICU_AFE_CTL_9_EN_SIN_2_BIAS_4_BIT ((u32)0x10000000)
+#define RICU_AFE_CTL_9_EN_SIN_2_BIAS_4_POS 28
+#define RICU_AFE_CTL_9_EN_SIN_2_BIAS_3_BIT ((u32)0x08000000)
+#define RICU_AFE_CTL_9_EN_SIN_2_BIAS_3_POS 27
+#define RICU_AFE_CTL_9_EN_SIN_2_BIAS_2_BIT ((u32)0x04000000)
+#define RICU_AFE_CTL_9_EN_SIN_2_BIAS_2_POS 26
+#define RICU_AFE_CTL_9_EN_SIN_2_BIAS_1_BIT ((u32)0x02000000)
+#define RICU_AFE_CTL_9_EN_SIN_2_BIAS_1_POS 25
+#define RICU_AFE_CTL_9_EN_SIN_2_BIAS_0_BIT ((u32)0x01000000)
+#define RICU_AFE_CTL_9_EN_SIN_2_BIAS_0_POS 24
+#define RICU_AFE_CTL_9_EN_DAC_REF_7_BIT ((u32)0x00800000)
+#define RICU_AFE_CTL_9_EN_DAC_REF_7_POS 23
+#define RICU_AFE_CTL_9_EN_DAC_REF_6_BIT ((u32)0x00400000)
+#define RICU_AFE_CTL_9_EN_DAC_REF_6_POS 22
+#define RICU_AFE_CTL_9_EN_DAC_REF_5_BIT ((u32)0x00200000)
+#define RICU_AFE_CTL_9_EN_DAC_REF_5_POS 21
+#define RICU_AFE_CTL_9_EN_DAC_REF_4_BIT ((u32)0x00100000)
+#define RICU_AFE_CTL_9_EN_DAC_REF_4_POS 20
+#define RICU_AFE_CTL_9_EN_DAC_REF_3_BIT ((u32)0x00080000)
+#define RICU_AFE_CTL_9_EN_DAC_REF_3_POS 19
+#define RICU_AFE_CTL_9_EN_DAC_REF_2_BIT ((u32)0x00040000)
+#define RICU_AFE_CTL_9_EN_DAC_REF_2_POS 18
+#define RICU_AFE_CTL_9_EN_DAC_REF_1_BIT ((u32)0x00020000)
+#define RICU_AFE_CTL_9_EN_DAC_REF_1_POS 17
+#define RICU_AFE_CTL_9_EN_DAC_REF_0_BIT ((u32)0x00010000)
+#define RICU_AFE_CTL_9_EN_DAC_REF_0_POS 16
+
+/*
+ * @brief AFE_CTL_10 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31 VC_LD7 0
+ * 30 VC_LD6 0
+ * 29 VC_LD5 0
+ * 28 VC_LD4 0
+ * 27 VC_LD3 0
+ * 26 VC_LD2 0
+ * 25 VC_LD1 0
+ * 24 VC_LD0 0
+ * 23 TWOS7 0
+ * 22 TWOS6 0
+ * 21 TWOS5 0
+ * 20 TWOS4 0
+ * 19 TWOS3 0
+ * 18 TWOS2 0
+ * 17 TWOS1 0
+ * 16 TWOS0 0
+ * 07 MINV7 1
+ * 06 MINV6 1
+ * 05 MINV5 1
+ * 04 MINV4 1
+ * 03 MINV3 1
+ * 02 MINV2 1
+ * 01 MINV1 1
+ * 00 MINV0 1
+ * </pre>
+ */
+#define RICU_AFE_CTL_10_ADDR (REG_RICU_BASE_ADDR + 0x00000038)
+#define RICU_AFE_CTL_10_OFFSET 0x00000038
+#define RICU_AFE_CTL_10_INDEX 0x0000000E
+#define RICU_AFE_CTL_10_RESET 0x000000FF
+
+static inline void ricu_afe_ctl_10_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, RICU_AFE_CTL_10_ADDR, value);
+}
+
+/*
+ * @brief AFE_CTL_12 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31:30 EOC_CTRL7 0x0
+ * 29:28 EOC_CTRL6 0x0
+ * 27:26 EOC_CTRL5 0x0
+ * 25:24 EOC_CTRL4 0x0
+ * 23:22 EOC_CTRL3 0x0
+ * 21:20 EOC_CTRL2 0x0
+ * 19:18 EOC_CTRL1 0x0
+ * 17:16 EOC_CTRL0 0x0
+ * 15:14 IC_REFSSF7 0x1
+ * 13:12 IC_REFSSF6 0x1
+ * 11:10 IC_REFSSF5 0x1
+ * 09:08 IC_REFSSF4 0x1
+ * 07:06 IC_REFSSF3 0x1
+ * 05:04 IC_REFSSF2 0x1
+ * 03:02 IC_REFSSF1 0x1
+ * 01:00 IC_REFSSF0 0x1
+ * </pre>
+ */
+#define RICU_AFE_CTL_12_ADDR (REG_RICU_BASE_ADDR + 0x00000040)
+#define RICU_AFE_CTL_12_OFFSET 0x00000040
+#define RICU_AFE_CTL_12_INDEX 0x00000010
+#define RICU_AFE_CTL_12_RESET 0x00005555
+
+static inline void ricu_afe_ctl_12_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, RICU_AFE_CTL_12_ADDR, value);
+}
+
+/*
+ * @brief AFE_CTL_17 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 30:28 VC_REF7 0x1
+ * 26:24 VC_REF6 0x1
+ * 22:20 VC_REF5 0x1
+ * 18:16 VC_REF4 0x1
+ * 14:12 VC_REF3 0x1
+ * 10:08 VC_REF2 0x1
+ * 06:04 VC_REF1 0x1
+ * 02:00 VC_REF0 0x1
+ * </pre>
+ */
+#define RICU_AFE_CTL_17_ADDR (REG_RICU_BASE_ADDR + 0x00000054)
+#define RICU_AFE_CTL_17_OFFSET 0x00000054
+#define RICU_AFE_CTL_17_INDEX 0x00000015
+#define RICU_AFE_CTL_17_RESET 0x11111111
+
+static inline void ricu_afe_ctl_17_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, RICU_AFE_CTL_17_ADDR, value);
+}
+
+/*
+ * @brief AFE_CTL_19 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31:28 COMP_CTRL7 0x4
+ * 27:24 COMP_CTRL6 0x4
+ * 23:20 COMP_CTRL5 0x4
+ * 19:16 COMP_CTRL4 0x4
+ * 15:12 COMP_CTRL3 0x4
+ * 11:08 COMP_CTRL2 0x4
+ * 07:04 COMP_CTRL1 0x4
+ * 03:00 COMP_CTRL0 0x4
+ * </pre>
+ */
+#define RICU_AFE_CTL_19_ADDR (REG_RICU_BASE_ADDR + 0x0000005C)
+#define RICU_AFE_CTL_19_OFFSET 0x0000005C
+#define RICU_AFE_CTL_19_INDEX 0x00000017
+#define RICU_AFE_CTL_19_RESET 0x44444444
+
+static inline void ricu_afe_ctl_19_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, RICU_AFE_CTL_19_ADDR, value);
+}
+
+/*
+ * @brief AFE_CTL_23 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 30:28 VC_LD_AVDI7 0x3
+ * 26:24 VC_LD_AVDI6 0x3
+ * 22:20 VC_LD_AVDI5 0x3
+ * 18:16 VC_LD_AVDI4 0x3
+ * 14:12 VC_LD_AVDI3 0x3
+ * 10:08 VC_LD_AVDI2 0x3
+ * 06:04 VC_LD_AVDI1 0x3
+ * 02:00 VC_LD_AVDI0 0x3
+ * </pre>
+ */
+#define RICU_AFE_CTL_23_ADDR (REG_RICU_BASE_ADDR + 0x0000006C)
+#define RICU_AFE_CTL_23_OFFSET 0x0000006C
+#define RICU_AFE_CTL_23_INDEX 0x0000001B
+#define RICU_AFE_CTL_23_RESET 0x33333333
+
+static inline void ricu_afe_ctl_23_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, RICU_AFE_CTL_23_ADDR, value);
+}
+
+/*
+ * @brief AFE_CTL_24 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 30:28 VC_LD_AVDQ7 0x3
+ * 26:24 VC_LD_AVDQ6 0x3
+ * 22:20 VC_LD_AVDQ5 0x3
+ * 18:16 VC_LD_AVDQ4 0x3
+ * 14:12 VC_LD_AVDQ3 0x3
+ * 10:08 VC_LD_AVDQ2 0x3
+ * 06:04 VC_LD_AVDQ1 0x3
+ * 02:00 VC_LD_AVDQ0 0x3
+ * </pre>
+ */
+#define RICU_AFE_CTL_24_ADDR (REG_RICU_BASE_ADDR + 0x00000070)
+#define RICU_AFE_CTL_24_OFFSET 0x00000070
+#define RICU_AFE_CTL_24_INDEX 0x0000001C
+#define RICU_AFE_CTL_24_RESET 0x33333333
+
+static inline void ricu_afe_ctl_24_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, RICU_AFE_CTL_24_ADDR, value);
+}
+
+/*
+ * @brief AFE_CTL_25 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 16 ROSEL0 0
+ * 14:08 RO_CTRLQ0 0x7
+ * 06:00 RO_CTRLI0 0x7
+ * </pre>
+ */
+#define RICU_AFE_CTL_25_ADDR (REG_RICU_BASE_ADDR + 0x00000074)
+#define RICU_AFE_CTL_25_OFFSET 0x00000074
+#define RICU_AFE_CTL_25_INDEX 0x0000001D
+#define RICU_AFE_CTL_25_RESET 0x00000707
+
+static inline void ricu_afe_ctl_25_pack(struct cl_chip *chip, u8 rosel0, u8 roctrlq0, u8 roctrli0)
+{
+ ASSERT_ERR_CHIP((((u32)rosel0 << 16) & ~((u32)0x00010000)) == 0);
+ ASSERT_ERR_CHIP((((u32)roctrlq0 << 8) & ~((u32)0x00007F00)) == 0);
+ ASSERT_ERR_CHIP((((u32)roctrli0 << 0) & ~((u32)0x0000007F)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTL_25_ADDR, ((u32)rosel0 << 16) | ((u32)roctrlq0 << 8) | ((u32)roctrli0 << 0));
+}
+
+/*
+ * @brief AFE_CTL_26 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 16 ROSEL1 0
+ * 14:08 RO_CTRLQ1 0x7
+ * 06:00 RO_CTRLI1 0x7
+ * </pre>
+ */
+#define RICU_AFE_CTL_26_ADDR (REG_RICU_BASE_ADDR + 0x00000078)
+#define RICU_AFE_CTL_26_OFFSET 0x00000078
+#define RICU_AFE_CTL_26_INDEX 0x0000001E
+#define RICU_AFE_CTL_26_RESET 0x00000707
+
+static inline void ricu_afe_ctl_26_pack(struct cl_chip *chip, u8 rosel1, u8 roctrlq1, u8 roctrli1)
+{
+ ASSERT_ERR_CHIP((((u32)rosel1 << 16) & ~((u32)0x00010000)) == 0);
+ ASSERT_ERR_CHIP((((u32)roctrlq1 << 8) & ~((u32)0x00007F00)) == 0);
+ ASSERT_ERR_CHIP((((u32)roctrli1 << 0) & ~((u32)0x0000007F)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTL_26_ADDR, ((u32)rosel1 << 16) | ((u32)roctrlq1 << 8) | ((u32)roctrli1 << 0));
+}
+
+/*
+ * @brief AFE_CTL_27 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 16 ROSEL2 0
+ * 14:08 RO_CTRLQ2 0x7
+ * 06:00 RO_CTRLI2 0x7
+ * </pre>
+ */
+#define RICU_AFE_CTL_27_ADDR (REG_RICU_BASE_ADDR + 0x0000007C)
+#define RICU_AFE_CTL_27_OFFSET 0x0000007C
+#define RICU_AFE_CTL_27_INDEX 0x0000001F
+#define RICU_AFE_CTL_27_RESET 0x00000707
+
+static inline void ricu_afe_ctl_27_pack(struct cl_chip *chip, u8 rosel2, u8 roctrlq2, u8 roctrli2)
+{
+ ASSERT_ERR_CHIP((((u32)rosel2 << 16) & ~((u32)0x00010000)) == 0);
+ ASSERT_ERR_CHIP((((u32)roctrlq2 << 8) & ~((u32)0x00007F00)) == 0);
+ ASSERT_ERR_CHIP((((u32)roctrli2 << 0) & ~((u32)0x0000007F)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTL_27_ADDR, ((u32)rosel2 << 16) | ((u32)roctrlq2 << 8) | ((u32)roctrli2 << 0));
+}
+
+/*
+ * @brief AFE_CTL_29 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 30:28 VC_CML7_I 0x5
+ * 26:24 VC_CML6_I 0x5
+ * 22:20 VC_CML5_I 0x5
+ * 18:16 VC_CML4_I 0x5
+ * 14:12 VC_CML3_I 0x5
+ * 10:08 VC_CML2_I 0x5
+ * 06:04 VC_CML1_I 0x5
+ * 02:00 VC_CML0_I 0x5
+ * </pre>
+ */
+#define RICU_AFE_CTL_29_ADDR (REG_RICU_BASE_ADDR + 0x00000084)
+#define RICU_AFE_CTL_29_OFFSET 0x00000084
+#define RICU_AFE_CTL_29_INDEX 0x00000021
+#define RICU_AFE_CTL_29_RESET 0x55555555
+
+static inline void ricu_afe_ctl_29_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, RICU_AFE_CTL_29_ADDR, value);
+}
+
+/*
+ * @brief AFE_CTL_30 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 30:28 VC_CML7_Q 0x5
+ * 26:24 VC_CML6_Q 0x5
+ * 22:20 VC_CML5_Q 0x5
+ * 18:16 VC_CML4_Q 0x5
+ * 14:12 VC_CML3_Q 0x5
+ * 10:08 VC_CML2_Q 0x5
+ * 06:04 VC_CML1_Q 0x5
+ * 02:00 VC_CML0_Q 0x5
+ * </pre>
+ */
+#define RICU_AFE_CTL_30_ADDR (REG_RICU_BASE_ADDR + 0x00000088)
+#define RICU_AFE_CTL_30_OFFSET 0x00000088
+#define RICU_AFE_CTL_30_INDEX 0x00000022
+#define RICU_AFE_CTL_30_RESET 0x55555555
+
+static inline void ricu_afe_ctl_30_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, RICU_AFE_CTL_30_ADDR, value);
+}
+
+/*
+ * @brief AFE_CTL_33 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 16 ROSEL3 0
+ * 14:08 RO_CTRL3_Q 0x7
+ * 06:00 RO_CTRL3_I 0x7
+ * </pre>
+ */
+#define RICU_AFE_CTL_33_ADDR (REG_RICU_BASE_ADDR + 0x00000094)
+#define RICU_AFE_CTL_33_OFFSET 0x00000094
+#define RICU_AFE_CTL_33_INDEX 0x00000025
+#define RICU_AFE_CTL_33_RESET 0x00000707
+
+static inline void ricu_afe_ctl_33_pack(struct cl_chip *chip, u8 rosel3, u8 roctrl3q, u8 roctrl3i)
+{
+ ASSERT_ERR_CHIP((((u32)rosel3 << 16) & ~((u32)0x00010000)) == 0);
+ ASSERT_ERR_CHIP((((u32)roctrl3q << 8) & ~((u32)0x00007F00)) == 0);
+ ASSERT_ERR_CHIP((((u32)roctrl3i << 0) & ~((u32)0x0000007F)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTL_33_ADDR, ((u32)rosel3 << 16) | ((u32)roctrl3q << 8) | ((u32)roctrl3i << 0));
+}
+
+/*
+ * @brief AFE_CTRL_34_PHY_0 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 06 PHY0_ADC_SB_IGNORE_FIFO_INDICATION 0
+ * 05:02 PHY0_ADC_SB_RD_DELAY 0x4
+ * 01:00 PHY0_ADC_SB_MODE 0x0
+ * </pre>
+ */
+#define RICU_AFE_CTRL_34_PHY_0_ADDR (REG_RICU_BASE_ADDR + 0x0000009C)
+#define RICU_AFE_CTRL_34_PHY_0_OFFSET 0x0000009C
+#define RICU_AFE_CTRL_34_PHY_0_INDEX 0x00000027
+#define RICU_AFE_CTRL_34_PHY_0_RESET 0x00000010
+
+static inline void ricu_afe_ctrl_34_phy_0_adc_sb_ignore_fifo_indication_setf(struct cl_chip *chip, u8 phy0adcsbignorefifoindication)
+{
+ ASSERT_ERR_CHIP((((u32)phy0adcsbignorefifoindication << 6) & ~((u32)0x00000040)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTRL_34_PHY_0_ADDR, (cl_reg_read_chip(chip, RICU_AFE_CTRL_34_PHY_0_ADDR) & ~((u32)0x00000040)) | ((u32)phy0adcsbignorefifoindication << 6));
+}
+
+static inline void ricu_afe_ctrl_34_phy_0_adc_sb_rd_delay_setf(struct cl_chip *chip, u8 phy0adcsbrddelay)
+{
+ ASSERT_ERR_CHIP((((u32)phy0adcsbrddelay << 2) & ~((u32)0x0000003C)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTRL_34_PHY_0_ADDR, (cl_reg_read_chip(chip, RICU_AFE_CTRL_34_PHY_0_ADDR) & ~((u32)0x0000003C)) | ((u32)phy0adcsbrddelay << 2));
+}
+
+/*
+ * @brief AFE_CTRL_36_PHY_0 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 07 PHY0_ADC_ALWAYS_EN_LD_IR 0
+ * 06 PHY0_ADC_ALWAYS_EN_LD_AVDQ 0
+ * 05 PHY0_ADC_ALWAYS_EN_LD_AVDI 0
+ * 04 PHY0_ADC_ALWAYS_EN_ADCQ 0
+ * 03 PHY0_ADC_ALWAYS_EN_ADCI 0
+ * 01 PHY0_HW_MODE_DAC 0
+ * 00 PHY0_HW_MODE_ADC 0
+ * </pre>
+ */
+#define RICU_AFE_CTRL_36_PHY_0_ADDR (REG_RICU_BASE_ADDR + 0x000000A0)
+#define RICU_AFE_CTRL_36_PHY_0_OFFSET 0x000000A0
+#define RICU_AFE_CTRL_36_PHY_0_INDEX 0x00000028
+#define RICU_AFE_CTRL_36_PHY_0_RESET 0x00000000
+
+static inline u32 ricu_afe_ctrl_36_phy_0_get(struct cl_chip *chip)
+{
+ return cl_reg_read_chip(chip, RICU_AFE_CTRL_36_PHY_0_ADDR);
+}
+
+static inline void ricu_afe_ctrl_36_phy_0_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, RICU_AFE_CTRL_36_PHY_0_ADDR, value);
+}
+
+/* Field definitions */
+#define RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_LD_IR_BIT ((u32)0x00000080)
+#define RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_LD_IR_POS 7
+#define RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_LD_AVDQ_BIT ((u32)0x00000040)
+#define RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_LD_AVDQ_POS 6
+#define RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_LD_AVDI_BIT ((u32)0x00000020)
+#define RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_LD_AVDI_POS 5
+#define RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_ADCQ_BIT ((u32)0x00000010)
+#define RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_ADCQ_POS 4
+#define RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_ADCI_BIT ((u32)0x00000008)
+#define RICU_AFE_CTRL_36_PHY_0_ADC_ALWAYS_EN_ADCI_POS 3
+#define RICU_AFE_CTRL_36_PHY_0_HW_MODE_DAC_BIT ((u32)0x00000002)
+#define RICU_AFE_CTRL_36_PHY_0_HW_MODE_DAC_POS 1
+#define RICU_AFE_CTRL_36_PHY_0_HW_MODE_ADC_BIT ((u32)0x00000001)
+#define RICU_AFE_CTRL_36_PHY_0_HW_MODE_ADC_POS 0
+
+static inline void ricu_afe_ctrl_36_phy_0_hw_mode_dac_setf(struct cl_chip *chip, u8 phy0hwmodedac)
+{
+ ASSERT_ERR_CHIP((((u32)phy0hwmodedac << 1) & ~((u32)0x00000002)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTRL_36_PHY_0_ADDR, (cl_reg_read_chip(chip, RICU_AFE_CTRL_36_PHY_0_ADDR) & ~((u32)0x00000002)) | ((u32)phy0hwmodedac << 1));
+}
+
+static inline void ricu_afe_ctrl_36_phy_0_hw_mode_adc_setf(struct cl_chip *chip, u8 phy0hwmodeadc)
+{
+ ASSERT_ERR_CHIP((((u32)phy0hwmodeadc << 0) & ~((u32)0x00000001)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTRL_36_PHY_0_ADDR, (cl_reg_read_chip(chip, RICU_AFE_CTRL_36_PHY_0_ADDR) & ~((u32)0x00000001)) | ((u32)phy0hwmodeadc << 0));
+}
+
+/*
+ * @brief AFE_CTRL_34_PHY_1 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 06 PHY1_ADC_SB_IGNORE_FIFO_INDICATION 0
+ * 05:02 PHY1_ADC_SB_RD_DELAY 0x4
+ * 01:00 PHY1_ADC_SB_MODE 0x0
+ * </pre>
+ */
+#define RICU_AFE_CTRL_34_PHY_1_ADDR (REG_RICU_BASE_ADDR + 0x000000A4)
+#define RICU_AFE_CTRL_34_PHY_1_OFFSET 0x000000A4
+#define RICU_AFE_CTRL_34_PHY_1_INDEX 0x00000029
+#define RICU_AFE_CTRL_34_PHY_1_RESET 0x00000010
+
+static inline void ricu_afe_ctrl_34_phy_1_adc_sb_ignore_fifo_indication_setf(struct cl_chip *chip, u8 phy1adcsbignorefifoindication)
+{
+ ASSERT_ERR_CHIP((((u32)phy1adcsbignorefifoindication << 6) & ~((u32)0x00000040)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTRL_34_PHY_1_ADDR, (cl_reg_read_chip(chip, RICU_AFE_CTRL_34_PHY_1_ADDR) & ~((u32)0x00000040)) | ((u32)phy1adcsbignorefifoindication << 6));
+}
+
+static inline void ricu_afe_ctrl_34_phy_1_adc_sb_rd_delay_setf(struct cl_chip *chip, u8 phy1adcsbrddelay)
+{
+ ASSERT_ERR_CHIP((((u32)phy1adcsbrddelay << 2) & ~((u32)0x0000003C)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTRL_34_PHY_1_ADDR, (cl_reg_read_chip(chip, RICU_AFE_CTRL_34_PHY_1_ADDR) & ~((u32)0x0000003C)) | ((u32)phy1adcsbrddelay << 2));
+}
+
+/*
+ * @brief AFE_CTRL_35_PHY_0 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 06 PHY0_DAC_SB_IGNORE_FIFO_INDICATION 0
+ * 05:02 PHY0_DAC_SB_RD_DELAY 0x1
+ * 01:00 PHY0_DAC_SB_MODE 0x0
+ * </pre>
+ */
+#define RICU_AFE_CTRL_35_PHY_0_ADDR (REG_RICU_BASE_ADDR + 0x000000A8)
+#define RICU_AFE_CTRL_35_PHY_0_OFFSET 0x000000A8
+#define RICU_AFE_CTRL_35_PHY_0_INDEX 0x0000002A
+#define RICU_AFE_CTRL_35_PHY_0_RESET 0x00000004
+
+static inline void ricu_afe_ctrl_35_phy_0_dac_sb_ignore_fifo_indication_setf(struct cl_chip *chip, u8 phy0dacsbignorefifoindication)
+{
+ ASSERT_ERR_CHIP((((u32)phy0dacsbignorefifoindication << 6) & ~((u32)0x00000040)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTRL_35_PHY_0_ADDR, (cl_reg_read_chip(chip, RICU_AFE_CTRL_35_PHY_0_ADDR) & ~((u32)0x00000040)) | ((u32)phy0dacsbignorefifoindication << 6));
+}
+
+static inline void ricu_afe_ctrl_35_phy_0_dac_sb_rd_delay_setf(struct cl_chip *chip, u8 phy0dacsbrddelay)
+{
+ ASSERT_ERR_CHIP((((u32)phy0dacsbrddelay << 2) & ~((u32)0x0000003C)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTRL_35_PHY_0_ADDR, (cl_reg_read_chip(chip, RICU_AFE_CTRL_35_PHY_0_ADDR) & ~((u32)0x0000003C)) | ((u32)phy0dacsbrddelay << 2));
+}
+
+/*
+ * @brief AFE_CTRL_35_PHY_1 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 06 PHY1_DAC_SB_IGNORE_FIFO_INDICATION 0
+ * 05:02 PHY1_DAC_SB_RD_DELAY 0x1
+ * 01:00 PHY1_DAC_SB_MODE 0x0
+ * </pre>
+ */
+#define RICU_AFE_CTRL_35_PHY_1_ADDR (REG_RICU_BASE_ADDR + 0x000000AC)
+#define RICU_AFE_CTRL_35_PHY_1_OFFSET 0x000000AC
+#define RICU_AFE_CTRL_35_PHY_1_INDEX 0x0000002B
+#define RICU_AFE_CTRL_35_PHY_1_RESET 0x00000004
+
+static inline void ricu_afe_ctrl_35_phy_1_dac_sb_ignore_fifo_indication_setf(struct cl_chip *chip, u8 phy1dacsbignorefifoindication)
+{
+ ASSERT_ERR_CHIP((((u32)phy1dacsbignorefifoindication << 6) & ~((u32)0x00000040)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTRL_35_PHY_1_ADDR, (cl_reg_read_chip(chip, RICU_AFE_CTRL_35_PHY_1_ADDR) & ~((u32)0x00000040)) | ((u32)phy1dacsbignorefifoindication << 6));
+}
+
+static inline void ricu_afe_ctrl_35_phy_1_dac_sb_rd_delay_setf(struct cl_chip *chip, u8 phy1dacsbrddelay)
+{
+ ASSERT_ERR_CHIP((((u32)phy1dacsbrddelay << 2) & ~((u32)0x0000003C)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTRL_35_PHY_1_ADDR, (cl_reg_read_chip(chip, RICU_AFE_CTRL_35_PHY_1_ADDR) & ~((u32)0x0000003C)) | ((u32)phy1dacsbrddelay << 2));
+}
+
+/*
+ * @brief AFE_CTRL_37_PHY_0 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 05 PHY0_EN_DAC5 0
+ * 04 PHY0_EN_DAC4 0
+ * 03 PHY0_EN_DAC3 0
+ * 02 PHY0_EN_DAC2 0
+ * 01 PHY0_EN_DAC1 0
+ * 00 PHY0_EN_DAC0 0
+ * </pre>
+ */
+#define RICU_AFE_CTRL_37_PHY_0_ADDR (REG_RICU_BASE_ADDR + 0x000000BC)
+#define RICU_AFE_CTRL_37_PHY_0_OFFSET 0x000000BC
+#define RICU_AFE_CTRL_37_PHY_0_INDEX 0x0000002F
+#define RICU_AFE_CTRL_37_PHY_0_RESET 0x00000000
+
+static inline u32 ricu_afe_ctrl_37_phy_0_get(struct cl_chip *chip)
+{
+ return cl_reg_read_chip(chip, RICU_AFE_CTRL_37_PHY_0_ADDR);
+}
+
+static inline void ricu_afe_ctrl_37_phy_0_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, RICU_AFE_CTRL_37_PHY_0_ADDR, value);
+}
+
+/* Field definitions */
+#define RICU_AFE_CTRL_37_PHY_0_EN_DAC_5_BIT ((u32)0x00000020)
+#define RICU_AFE_CTRL_37_PHY_0_EN_DAC_5_POS 5
+#define RICU_AFE_CTRL_37_PHY_0_EN_DAC_4_BIT ((u32)0x00000010)
+#define RICU_AFE_CTRL_37_PHY_0_EN_DAC_4_POS 4
+#define RICU_AFE_CTRL_37_PHY_0_EN_DAC_3_BIT ((u32)0x00000008)
+#define RICU_AFE_CTRL_37_PHY_0_EN_DAC_3_POS 3
+#define RICU_AFE_CTRL_37_PHY_0_EN_DAC_2_BIT ((u32)0x00000004)
+#define RICU_AFE_CTRL_37_PHY_0_EN_DAC_2_POS 2
+#define RICU_AFE_CTRL_37_PHY_0_EN_DAC_1_BIT ((u32)0x00000002)
+#define RICU_AFE_CTRL_37_PHY_0_EN_DAC_1_POS 1
+#define RICU_AFE_CTRL_37_PHY_0_EN_DAC_0_BIT ((u32)0x00000001)
+#define RICU_AFE_CTRL_37_PHY_0_EN_DAC_0_POS 0
+
+/*
+ * @brief AFE_CTRL_37_PHY_1 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 05 PHY1_EN_DAC5 0
+ * 04 PHY1_EN_DAC4 0
+ * 03 PHY1_EN_DAC3 0
+ * 02 PHY1_EN_DAC2 0
+ * 01 PHY1_EN_DAC1 0
+ * 00 PHY1_EN_DAC0 0
+ * </pre>
+ */
+#define RICU_AFE_CTRL_37_PHY_1_ADDR (REG_RICU_BASE_ADDR + 0x000000C0)
+#define RICU_AFE_CTRL_37_PHY_1_OFFSET 0x000000C0
+#define RICU_AFE_CTRL_37_PHY_1_INDEX 0x00000030
+#define RICU_AFE_CTRL_37_PHY_1_RESET 0x00000000
+
+static inline u32 ricu_afe_ctrl_37_phy_1_get(struct cl_chip *chip)
+{
+ return cl_reg_read_chip(chip, RICU_AFE_CTRL_37_PHY_1_ADDR);
+}
+
+static inline void ricu_afe_ctrl_37_phy_1_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, RICU_AFE_CTRL_37_PHY_1_ADDR, value);
+}
+
+/* Field definitions */
+#define RICU_AFE_CTRL_37_PHY_1_EN_DAC_5_BIT ((u32)0x00000020)
+#define RICU_AFE_CTRL_37_PHY_1_EN_DAC_5_POS 5
+#define RICU_AFE_CTRL_37_PHY_1_EN_DAC_4_BIT ((u32)0x00000010)
+#define RICU_AFE_CTRL_37_PHY_1_EN_DAC_4_POS 4
+#define RICU_AFE_CTRL_37_PHY_1_EN_DAC_3_BIT ((u32)0x00000008)
+#define RICU_AFE_CTRL_37_PHY_1_EN_DAC_3_POS 3
+#define RICU_AFE_CTRL_37_PHY_1_EN_DAC_2_BIT ((u32)0x00000004)
+#define RICU_AFE_CTRL_37_PHY_1_EN_DAC_2_POS 2
+#define RICU_AFE_CTRL_37_PHY_1_EN_DAC_1_BIT ((u32)0x00000002)
+#define RICU_AFE_CTRL_37_PHY_1_EN_DAC_1_POS 1
+#define RICU_AFE_CTRL_37_PHY_1_EN_DAC_0_BIT ((u32)0x00000001)
+#define RICU_AFE_CTRL_37_PHY_1_EN_DAC_0_POS 0
+
+/*
+ * @brief AFE_CTRL_39 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 16 ROSEL4 0
+ * 14:08 RO_CTRLQ4 0x7
+ * 06:00 RO_CTRLI4 0x7
+ * </pre>
+ */
+#define RICU_AFE_CTRL_39_ADDR (REG_RICU_BASE_ADDR + 0x000000CC)
+#define RICU_AFE_CTRL_39_OFFSET 0x000000CC
+#define RICU_AFE_CTRL_39_INDEX 0x00000033
+#define RICU_AFE_CTRL_39_RESET 0x00000707
+
+static inline void ricu_afe_ctrl_39_pack(struct cl_chip *chip, u8 rosel4, u8 roctrlq4, u8 roctrli4)
+{
+ ASSERT_ERR_CHIP((((u32)rosel4 << 16) & ~((u32)0x00010000)) == 0);
+ ASSERT_ERR_CHIP((((u32)roctrlq4 << 8) & ~((u32)0x00007F00)) == 0);
+ ASSERT_ERR_CHIP((((u32)roctrli4 << 0) & ~((u32)0x0000007F)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTRL_39_ADDR, ((u32)rosel4 << 16) | ((u32)roctrlq4 << 8) | ((u32)roctrli4 << 0));
+}
+
+/*
+ * @brief AFE_CTRL_40 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 16 ROSEL5 0
+ * 14:08 RO_CTRLQ5 0x7
+ * 06:00 RO_CTRLI5 0x7
+ * </pre>
+ */
+#define RICU_AFE_CTRL_40_ADDR (REG_RICU_BASE_ADDR + 0x000000D0)
+#define RICU_AFE_CTRL_40_OFFSET 0x000000D0
+#define RICU_AFE_CTRL_40_INDEX 0x00000034
+#define RICU_AFE_CTRL_40_RESET 0x00000707
+
+static inline void ricu_afe_ctrl_40_pack(struct cl_chip *chip, u8 rosel5, u8 roctrlq5, u8 roctrli5)
+{
+ ASSERT_ERR_CHIP((((u32)rosel5 << 16) & ~((u32)0x00010000)) == 0);
+ ASSERT_ERR_CHIP((((u32)roctrlq5 << 8) & ~((u32)0x00007F00)) == 0);
+ ASSERT_ERR_CHIP((((u32)roctrli5 << 0) & ~((u32)0x0000007F)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTRL_40_ADDR, ((u32)rosel5 << 16) | ((u32)roctrlq5 << 8) | ((u32)roctrli5 << 0));
+}
+
+/*
+ * @brief AFE_CTRL_41 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 16 ROSEL6 0
+ * 14:08 RO_CTRLQ6 0x7
+ * 06:00 RO_CTRLI6 0x7
+ * </pre>
+ */
+#define RICU_AFE_CTRL_41_ADDR (REG_RICU_BASE_ADDR + 0x000000D4)
+#define RICU_AFE_CTRL_41_OFFSET 0x000000D4
+#define RICU_AFE_CTRL_41_INDEX 0x00000035
+#define RICU_AFE_CTRL_41_RESET 0x00000707
+
+static inline void ricu_afe_ctrl_41_pack(struct cl_chip *chip, u8 rosel6, u8 roctrlq6, u8 roctrli6)
+{
+ ASSERT_ERR_CHIP((((u32)rosel6 << 16) & ~((u32)0x00010000)) == 0);
+ ASSERT_ERR_CHIP((((u32)roctrlq6 << 8) & ~((u32)0x00007F00)) == 0);
+ ASSERT_ERR_CHIP((((u32)roctrli6 << 0) & ~((u32)0x0000007F)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTRL_41_ADDR, ((u32)rosel6 << 16) | ((u32)roctrlq6 << 8) | ((u32)roctrli6 << 0));
+}
+
+/*
+ * @brief AFE_CTRL_42 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 16 ROSEL7 0
+ * 14:08 RO_CTRLQ7 0x7
+ * 06:00 RO_CTRLI7 0x7
+ * </pre>
+ */
+#define RICU_AFE_CTRL_42_ADDR (REG_RICU_BASE_ADDR + 0x000000D8)
+#define RICU_AFE_CTRL_42_OFFSET 0x000000D8
+#define RICU_AFE_CTRL_42_INDEX 0x00000036
+#define RICU_AFE_CTRL_42_RESET 0x00000707
+
+static inline void ricu_afe_ctrl_42_pack(struct cl_chip *chip, u8 rosel7, u8 roctrlq7, u8 roctrli7)
+{
+ ASSERT_ERR_CHIP((((u32)rosel7 << 16) & ~((u32)0x00010000)) == 0);
+ ASSERT_ERR_CHIP((((u32)roctrlq7 << 8) & ~((u32)0x00007F00)) == 0);
+ ASSERT_ERR_CHIP((((u32)roctrli7 << 0) & ~((u32)0x0000007F)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTRL_42_ADDR, ((u32)rosel7 << 16) | ((u32)roctrlq7 << 8) | ((u32)roctrli7 << 0));
+}
+
+/*
+ * @brief AFE_CTRL_43 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 01:00 FREQ_SEL 0x3
+ * </pre>
+ */
+#define RICU_AFE_CTRL_43_ADDR (REG_RICU_BASE_ADDR + 0x000000DC)
+#define RICU_AFE_CTRL_43_OFFSET 0x000000DC
+#define RICU_AFE_CTRL_43_INDEX 0x00000037
+#define RICU_AFE_CTRL_43_RESET 0x00000003
+
+static inline void ricu_afe_ctrl_43_freq_sel_setf(struct cl_chip *chip, u8 freqsel)
+{
+ ASSERT_ERR_CHIP((((u32)freqsel << 0) & ~((u32)0x00000003)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTRL_43_ADDR, (u32)freqsel << 0);
+}
+
+/*
+ * @brief AFE_CTRL_44 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 01:00 CDB_FREQ_SEL 0x3
+ * </pre>
+ */
+#define RICU_AFE_CTRL_44_ADDR (REG_RICU_BASE_ADDR + 0x000000E0)
+#define RICU_AFE_CTRL_44_OFFSET 0x000000E0
+#define RICU_AFE_CTRL_44_INDEX 0x00000038
+#define RICU_AFE_CTRL_44_RESET 0x00000003
+
+static inline void ricu_afe_ctrl_44_cdb_freq_sel_setf(struct cl_chip *chip, u8 cdbfreqsel)
+{
+ ASSERT_ERR_CHIP((((u32)cdbfreqsel << 0) & ~((u32)0x00000003)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTRL_44_ADDR, (u32)cdbfreqsel << 0);
+}
+
+/*
+ * @brief SPI_CLK_CTRL register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 05:00 SPI_CLK_BITMAP 0xE
+ * </pre>
+ */
+#define RICU_SPI_CLK_CTRL_ADDR (REG_RICU_BASE_ADDR + 0x000000E4)
+#define RICU_SPI_CLK_CTRL_OFFSET 0x000000E4
+#define RICU_SPI_CLK_CTRL_INDEX 0x00000039
+#define RICU_SPI_CLK_CTRL_RESET 0x0000000E
+
+static inline void ricu_spi_clk_ctrl_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, RICU_SPI_CLK_CTRL_ADDR, value);
+}
+
+/*
+ * @brief FEM_CONF_0 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 23:20 FEM5_CTL_SEL 0x5
+ * 19:16 FEM4_CTL_SEL 0x4
+ * 15:12 FEM3_CTL_SEL 0x3
+ * 11:08 FEM2_CTL_SEL 0x2
+ * 07:04 FEM1_CTL_SEL 0x1
+ * 03:00 FEM0_CTL_SEL 0x0
+ * </pre>
+ */
+#define RICU_FEM_CONF_0_ADDR (REG_RICU_BASE_ADDR + 0x000000F0)
+#define RICU_FEM_CONF_0_OFFSET 0x000000F0
+#define RICU_FEM_CONF_0_INDEX 0x0000003C
+#define RICU_FEM_CONF_0_RESET 0x00543210
+
+static inline void ricu_fem_conf_0_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, RICU_FEM_CONF_0_ADDR, value);
+}
+
+/*
+ * @brief FEM_CONF_1 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 23:20 FEM11_CTL_SEL 0xd
+ * 19:16 FEM10_CTL_SEL 0xc
+ * 15:12 FEM9_CTL_SEL 0xb
+ * 11:08 FEM8_CTL_SEL 0xa
+ * 07:04 FEM7_CTL_SEL 0x9
+ * 03:00 FEM6_CTL_SEL 0x8
+ * </pre>
+ */
+#define RICU_FEM_CONF_1_ADDR (REG_RICU_BASE_ADDR + 0x000000F4)
+#define RICU_FEM_CONF_1_OFFSET 0x000000F4
+#define RICU_FEM_CONF_1_INDEX 0x0000003D
+#define RICU_FEM_CONF_1_RESET 0x00DCBA98
+
+static inline void ricu_fem_conf_1_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, RICU_FEM_CONF_1_ADDR, value);
+}
+
+/*
+ * @brief AFE_CTRL_36_PHY_1 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 07 PHY1_ADC_ALWAYS_EN_LD_IR 0
+ * 06 PHY1_ADC_ALWAYS_EN_LD_AVDQ 0
+ * 05 PHY1_ADC_ALWAYS_EN_LD_AVDI 0
+ * 04 PHY1_ADC_ALWAYS_EN_ADCQ 0
+ * 03 PHY1_ADC_ALWAYS_EN_ADCI 0
+ * 01 PHY1_HW_MODE_DAC 0
+ * 00 PHY1_HW_MODE_ADC 0
+ * </pre>
+ */
+#define RICU_AFE_CTRL_36_PHY_1_ADDR (REG_RICU_BASE_ADDR + 0x000000F8)
+#define RICU_AFE_CTRL_36_PHY_1_OFFSET 0x000000F8
+#define RICU_AFE_CTRL_36_PHY_1_INDEX 0x0000003E
+#define RICU_AFE_CTRL_36_PHY_1_RESET 0x00000000
+
+static inline u32 ricu_afe_ctrl_36_phy_1_get(struct cl_chip *chip)
+{
+ return cl_reg_read_chip(chip, RICU_AFE_CTRL_36_PHY_1_ADDR);
+}
+
+static inline void ricu_afe_ctrl_36_phy_1_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, RICU_AFE_CTRL_36_PHY_1_ADDR, value);
+}
+
+/* Field definitions */
+#define RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_LD_IR_BIT ((u32)0x00000080)
+#define RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_LD_IR_POS 7
+#define RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_LD_AVDQ_BIT ((u32)0x00000040)
+#define RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_LD_AVDQ_POS 6
+#define RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_LD_AVDI_BIT ((u32)0x00000020)
+#define RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_LD_AVDI_POS 5
+#define RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_ADCQ_BIT ((u32)0x00000010)
+#define RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_ADCQ_POS 4
+#define RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_ADCI_BIT ((u32)0x00000008)
+#define RICU_AFE_CTRL_36_PHY_1_ADC_ALWAYS_EN_ADCI_POS 3
+#define RICU_AFE_CTRL_36_PHY_1_HW_MODE_DAC_BIT ((u32)0x00000002)
+#define RICU_AFE_CTRL_36_PHY_1_HW_MODE_DAC_POS 1
+#define RICU_AFE_CTRL_36_PHY_1_HW_MODE_ADC_BIT ((u32)0x00000001)
+#define RICU_AFE_CTRL_36_PHY_1_HW_MODE_ADC_POS 0
+
+static inline void ricu_afe_ctrl_36_phy_1_hw_mode_dac_setf(struct cl_chip *chip, u8 phy1hwmodedac)
+{
+ ASSERT_ERR_CHIP((((u32)phy1hwmodedac << 1) & ~((u32)0x00000002)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTRL_36_PHY_1_ADDR, (cl_reg_read_chip(chip, RICU_AFE_CTRL_36_PHY_1_ADDR) & ~((u32)0x00000002)) | ((u32)phy1hwmodedac << 1));
+}
+
+static inline void ricu_afe_ctrl_36_phy_1_hw_mode_adc_setf(struct cl_chip *chip, u8 phy1hwmodeadc)
+{
+ ASSERT_ERR_CHIP((((u32)phy1hwmodeadc << 0) & ~((u32)0x00000001)) == 0);
+ cl_reg_write_chip(chip, RICU_AFE_CTRL_36_PHY_1_ADDR, (cl_reg_read_chip(chip, RICU_AFE_CTRL_36_PHY_1_ADDR) & ~((u32)0x00000001)) | ((u32)phy1hwmodeadc << 0));
+}
+
+/*
+ * @brief AFE_ADC_CH_ALLOC register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 07:00 AFE_ADC_CH_ALLOC 0xFF
+ * </pre>
+ */
+#define RICU_AFE_ADC_CH_ALLOC_ADDR (REG_RICU_BASE_ADDR + 0x000000FC)
+#define RICU_AFE_ADC_CH_ALLOC_OFFSET 0x000000FC
+#define RICU_AFE_ADC_CH_ALLOC_INDEX 0x0000003F
+#define RICU_AFE_ADC_CH_ALLOC_RESET 0x000000FF
+
+/* Field definitions */
+#define RICU_AFE_ADC_CH_ALLOC_AFE_ADC_CH_ALLOC_MASK ((u32)0x000000FF)
+#define RICU_AFE_ADC_CH_ALLOC_AFE_ADC_CH_ALLOC_LSB 0
+#define RICU_AFE_ADC_CH_ALLOC_AFE_ADC_CH_ALLOC_WIDTH ((u32)0x00000008)
+
+static inline void ricu_afe_adc_ch_alloc_afe_adc_ch_alloc_setf(struct cl_chip *chip, u8 afeadcchalloc)
+{
+ cl_reg_write_chip(chip, RICU_AFE_ADC_CH_ALLOC_ADDR, (u32)afeadcchalloc << 0);
+}
+
+#endif /*CL_REG_RICU_H */
--
2.30.0
________________________________
The information transmitted is intended only for the person or entity to which it is addressed and may contain confidential and/or privileged material. Any retransmission, dissemination, copying or other use of, or taking of any action in reliance upon this information is prohibited. If you received this in error, please contact the sender and delete the material from any computer. Nothing contained herein shall be deemed as a representation, warranty or a commitment by Celeno. No warranties are expressed or implied, including, but not limited to, any implied warranties of non-infringement, merchantability and fitness for a particular purpose.
________________________________
