From: Viktor Barna <viktor.barna@xxxxxxxxxx>
(Part of the split. Please, take a look at the cover letter for more
details).
Signed-off-by: Viktor Barna <viktor.barna@xxxxxxxxxx>
---
.../wireless/celeno/cl8k/reg/reg_otp_pvt.h | 219 ++++++++++++++++++
1 file changed, 219 insertions(+)
create mode 100644 drivers/net/wireless/celeno/cl8k/reg/reg_otp_pvt.h
diff --git a/drivers/net/wireless/celeno/cl8k/reg/reg_otp_pvt.h b/drivers/net/wireless/celeno/cl8k/reg/reg_otp_pvt.h
new file mode 100644
index 000000000000..18866c1c3710
--- /dev/null
+++ b/drivers/net/wireless/celeno/cl8k/reg/reg_otp_pvt.h
@@ -0,0 +1,219 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright(c) 2019-2021, Celeno Communications Ltd. */
+
+#ifndef CL_REG_OTP_PVT
+#define CL_REG_OTP_PVT
+
+#include <linux/types.h>
+#include "reg/reg_access.h"
+#include "chip.h"
+
+#define REG_OTP_PVT_BASE_ADDR 0x007C9000
+
+/*
+ * @brief OTP_CMD register definition
+ * OTP command register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 28 OTP_PR_ACC 0
+ * 24 OTP_ABORT_CLR 0
+ * 16 OTP_READY 1
+ * 12 OTP_WRITE_FAILED 0
+ * 01:00 OTP_CMD 0x0
+ * </pre>
+ */
+#define OTP_PVT_OTP_CMD_ADDR (REG_OTP_PVT_BASE_ADDR + 0x00000000)
+#define OTP_PVT_OTP_CMD_OFFSET 0x00000000
+#define OTP_PVT_OTP_CMD_INDEX 0x00000000
+#define OTP_PVT_OTP_CMD_RESET 0x00010000
+
+static inline u8 otp_pvt_otp_cmd_otp_pr_acc_getf(struct cl_chip *chip)
+{
+ u32 local_val = cl_reg_read_chip(chip, OTP_PVT_OTP_CMD_ADDR);
+
+ return ((local_val & ((u32)0x10000000)) >> 28);
+}
+
+static inline u8 otp_pvt_otp_cmd_otp_ready_getf(struct cl_chip *chip)
+{
+ u32 local_val = cl_reg_read_chip(chip, OTP_PVT_OTP_CMD_ADDR);
+
+ return ((local_val & ((u32)0x00010000)) >> 16);
+}
+
+static inline u8 otp_pvt_otp_cmd_otp_write_failed_getf(struct cl_chip *chip)
+{
+ u32 local_val = cl_reg_read_chip(chip, OTP_PVT_OTP_CMD_ADDR);
+
+ return ((local_val & ((u32)0x00001000)) >> 12);
+}
+
+static inline void otp_pvt_otp_cmd_otp_cmd_setf(struct cl_chip *chip, u8 otpcmd)
+{
+ ASSERT_ERR_CHIP((((u32)otpcmd << 0) & ~((u32)0x00000003)) == 0);
+ cl_reg_write_chip(chip, OTP_PVT_OTP_CMD_ADDR,
+ (cl_reg_read_chip(chip, OTP_PVT_OTP_CMD_ADDR) & ~((u32)0x00000003)) | ((u32)otpcmd << 0));
+}
+
+/*
+ * @brief OTP_READ_VAL register definition
+ * OTP read value register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31:00 OTP_READ_VAL 0x0
+ * </pre>
+ */
+#define OTP_PVT_OTP_READ_VAL_ADDR (REG_OTP_PVT_BASE_ADDR + 0x00000004)
+#define OTP_PVT_OTP_READ_VAL_OFFSET 0x00000004
+#define OTP_PVT_OTP_READ_VAL_INDEX 0x00000001
+#define OTP_PVT_OTP_READ_VAL_RESET 0x00000000
+
+static inline u32 otp_pvt_otp_read_val_get(struct cl_chip *chip)
+{
+ return cl_reg_read_chip(chip, OTP_PVT_OTP_READ_VAL_ADDR);
+}
+
+/*
+ * @brief OTP_ADDR register definition
+ * OTP address register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 12:00 OTP_ADDR 0x0
+ * </pre>
+ */
+#define OTP_PVT_OTP_ADDR_ADDR (REG_OTP_PVT_BASE_ADDR + 0x00000008)
+#define OTP_PVT_OTP_ADDR_OFFSET 0x00000008
+#define OTP_PVT_OTP_ADDR_INDEX 0x00000002
+#define OTP_PVT_OTP_ADDR_RESET 0x00000000
+
+static inline void otp_pvt_otp_addr_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, OTP_PVT_OTP_ADDR_ADDR, value);
+}
+
+/*
+ * @brief OTP_TIMINGS_1 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31:25 otp_t_CPH 0xa
+ * 24:18 t_PES 0xa
+ * 17:16 t_UT 0x0
+ * 15:08 t_RW 0x15
+ * 07:00 t_CSRT 0x29
+ * </pre>
+ */
+#define OTP_PVT_OTP_TIMINGS_1_ADDR (REG_OTP_PVT_BASE_ADDR + 0x0000000C)
+#define OTP_PVT_OTP_TIMINGS_1_OFFSET 0x0000000C
+#define OTP_PVT_OTP_TIMINGS_1_INDEX 0x00000003
+#define OTP_PVT_OTP_TIMINGS_1_RESET 0x14281529
+
+static inline void otp_pvt_otp_timings_1_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, OTP_PVT_OTP_TIMINGS_1_ADDR, value);
+}
+
+/*
+ * @brief OTP_TIMINGS_2 register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 30:26 t_RD 0x5
+ * 25:16 t_PW 0x50
+ * 15:08 t_PEH 0x20
+ * 07:00 t_CPS 0x20
+ * </pre>
+ */
+#define OTP_PVT_OTP_TIMINGS_2_ADDR (REG_OTP_PVT_BASE_ADDR + 0x00000010)
+#define OTP_PVT_OTP_TIMINGS_2_OFFSET 0x00000010
+#define OTP_PVT_OTP_TIMINGS_2_INDEX 0x00000004
+#define OTP_PVT_OTP_TIMINGS_2_RESET 0x14502020
+
+static inline void otp_pvt_otp_timings_2_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, OTP_PVT_OTP_TIMINGS_2_ADDR, value);
+}
+
+/*
+ * @brief OTP_WRITE_VAL register definition
+ * OTP write value register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 00 OTP_WRITE_VAL 0
+ * </pre>
+ */
+#define OTP_PVT_OTP_WRITE_VAL_ADDR (REG_OTP_PVT_BASE_ADDR + 0x00000014)
+#define OTP_PVT_OTP_WRITE_VAL_OFFSET 0x00000014
+#define OTP_PVT_OTP_WRITE_VAL_INDEX 0x00000005
+#define OTP_PVT_OTP_WRITE_VAL_RESET 0x00000000
+
+static inline void otp_pvt_otp_write_val_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, OTP_PVT_OTP_WRITE_VAL_ADDR, value);
+}
+
+/*
+ * @brief OTP_KEY register definition
+ * OTP key register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31:00 OTP_KEY 0x0
+ * </pre>
+ */
+#define OTP_PVT_OTP_KEY_ADDR (REG_OTP_PVT_BASE_ADDR + 0x00000018)
+#define OTP_PVT_OTP_KEY_OFFSET 0x00000018
+#define OTP_PVT_OTP_KEY_INDEX 0x00000006
+#define OTP_PVT_OTP_KEY_RESET 0x00000000
+
+static inline void otp_pvt_otp_key_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, OTP_PVT_OTP_KEY_ADDR, value);
+}
+
+/*
+ * @brief OTP_CLK_DIV register definition
+ * OTP clock divisor register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 08:00 OTP_CLK_DIV 0x1
+ * </pre>
+ */
+#define OTP_PVT_OTP_CLK_DIV_ADDR (REG_OTP_PVT_BASE_ADDR + 0x0000001C)
+#define OTP_PVT_OTP_CLK_DIV_OFFSET 0x0000001C
+#define OTP_PVT_OTP_CLK_DIV_INDEX 0x00000007
+#define OTP_PVT_OTP_CLK_DIV_RESET 0x00000001
+
+static inline void otp_pvt_otp_clk_div_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, OTP_PVT_OTP_CLK_DIV_ADDR, value);
+}
+
+/*
+ * @brief OTP_PROTECT register definition
+ * OTP address protection register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 01 OTP_PR_DIS 0
+ * 00 OTP_PR_SEL 0
+ * </pre>
+ */
+#define OTP_PVT_OTP_PROTECT_ADDR (REG_OTP_PVT_BASE_ADDR + 0x00000024)
+#define OTP_PVT_OTP_PROTECT_OFFSET 0x00000024
+#define OTP_PVT_OTP_PROTECT_INDEX 0x00000009
+#define OTP_PVT_OTP_PROTECT_RESET 0x00000000
+
+static inline void otp_pvt_otp_protect_otp_pr_dis_setf(struct cl_chip *chip, u8 otpprdis)
+{
+ ASSERT_ERR_CHIP((((u32)otpprdis << 1) & ~((u32)0x00000002)) == 0);
+ cl_reg_write_chip(chip, OTP_PVT_OTP_PROTECT_ADDR,
+ (cl_reg_read_chip(chip, OTP_PVT_OTP_PROTECT_ADDR) & ~((u32)0x00000002)) | ((u32)otpprdis << 1));
+}
+
+#endif /* CL_REG_OTP_PVT */
--
2.30.0
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