From: Viktor Barna <viktor.barna@xxxxxxxxxx>
(Part of the split. Please, take a look at the cover letter for more
details).
Signed-off-by: Viktor Barna <viktor.barna@xxxxxxxxxx>
---
.../net/wireless/celeno/cl8k/reg/reg_mac_hw.h | 490 ++++++++++++++++++
1 file changed, 490 insertions(+)
create mode 100644 drivers/net/wireless/celeno/cl8k/reg/reg_mac_hw.h
diff --git a/drivers/net/wireless/celeno/cl8k/reg/reg_mac_hw.h b/drivers/net/wireless/celeno/cl8k/reg/reg_mac_hw.h
new file mode 100644
index 000000000000..50ee26b2c5fa
--- /dev/null
+++ b/drivers/net/wireless/celeno/cl8k/reg/reg_mac_hw.h
@@ -0,0 +1,490 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright(c) 2019-2021, Celeno Communications Ltd. */
+
+#ifndef CL_REG_MAC_HW_H
+#define CL_REG_MAC_HW_H
+
+#include <linux/types.h>
+#include "reg/reg_access.h"
+#include "hw.h"
+
+/*
+ * @brief STATE_CNTRL register definition
+ * This register controls the core's state transitions. register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 07:04 NEXT_STATE 0x0
+ * 03:00 CURRENT_STATE 0x0
+ * </pre>
+ */
+#define MAC_HW_STATE_CNTRL_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000038)
+#define MAC_HW_STATE_CNTRL_OFFSET 0x00000038
+#define MAC_HW_STATE_CNTRL_INDEX 0x0000000E
+#define MAC_HW_STATE_CNTRL_RESET 0x00000000
+
+/* Field definitions */
+#define MAC_HW_STATE_CNTRL_NEXT_STATE_MASK ((u32)0x000000F0)
+#define MAC_HW_STATE_CNTRL_NEXT_STATE_LSB 4
+#define MAC_HW_STATE_CNTRL_NEXT_STATE_WIDTH ((u32)0x00000004)
+#define MAC_HW_STATE_CNTRL_CURRENT_STATE_MASK ((u32)0x0000000F)
+#define MAC_HW_STATE_CNTRL_CURRENT_STATE_LSB 0
+#define MAC_HW_STATE_CNTRL_CURRENT_STATE_WIDTH ((u32)0x00000004)
+
+static inline void mac_hw_state_cntrl_next_state_setf(struct cl_hw *cl_hw, u8 nextstate)
+{
+ ASSERT_ERR((((u32)nextstate << 4) & ~((u32)0x000000F0)) == 0);
+ cl_reg_write(cl_hw, MAC_HW_STATE_CNTRL_ADDR,
+ (cl_reg_read(cl_hw, MAC_HW_STATE_CNTRL_ADDR) & ~((u32)0x000000F0)) | ((u32)nextstate << 4));
+}
+
+/*
+ * @brief MAC_CNTRL_1 register definition
+ * Contains various settings for controlling the operation of the core. register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31 EOF_PAD_FOR_HE 1
+ * 30 EOF_PAD_FOR_VHT 0
+ * 29:28 IMPLICIT_BF_INT_CONF 0x0
+ * 27 DISABLE_BFR_RESP 0
+ * 26 RX_RIFS_EN 0
+ * 25 TSF_MGT_DISABLE 0
+ * 24 TSF_UPDATED_BY_SW 0
+ * 22 MAC_DETECT_UNDERRUN_EN 0
+ * 21 DISABLE_MU_CTS_RESP 0
+ * 20 BQRP_RESP_BY_FW 0
+ * 19 BSRP_RESP_BY_FW 0
+ * 18 ENABLE_NORMAL_ACK_RESP_IN_HE_MU_W_TRIG 0
+ * 17 DISABLE_NORMAL_ACK_RESP_IN_HE_MU_WO_TRIG 0
+ * 16:14 ABGN_MODE 0x3
+ * 13 KEY_STO_RAM_RESET 0
+ * 12 MIB_TABLE_RESET 0
+ * 11 RATE_CONTROLLER_MPIF 1
+ * 10 DISABLE_BA_RESP 0
+ * 09 DISABLE_CTS_RESP 0
+ * 08 DISABLE_ACK_RESP 0
+ * 07 ACTIVE_CLK_GATING 1
+ * 06 ENABLE_LP_CLK_SWITCH 0
+ * 05 FORCE_MSTA_BA 0
+ * 04 DISABLE_FAST_COMPARE 0
+ * 03 CFP_AWARE 0
+ * 02 PWR_MGT 0
+ * 01 AP 0
+ * 00 BSS_TYPE 1
+ * </pre>
+ */
+#define MAC_HW_MAC_CNTRL_1_ADDR (REG_MAC_HW_BASE_ADDR + 0x0000004C)
+#define MAC_HW_MAC_CNTRL_1_OFFSET 0x0000004C
+#define MAC_HW_MAC_CNTRL_1_INDEX 0x00000013
+#define MAC_HW_MAC_CNTRL_1_RESET 0x8000C881
+
+/* Field definitions */
+#define MAC_HW_MAC_CNTRL_1_EOF_PAD_FOR_HE_BIT ((u32)0x80000000)
+#define MAC_HW_MAC_CNTRL_1_EOF_PAD_FOR_HE_POS 31
+#define MAC_HW_MAC_CNTRL_1_EOF_PAD_FOR_VHT_BIT ((u32)0x40000000)
+#define MAC_HW_MAC_CNTRL_1_EOF_PAD_FOR_VHT_POS 30
+#define MAC_HW_MAC_CNTRL_1_IMPLICIT_BF_INT_CONF_MASK ((u32)0x30000000)
+#define MAC_HW_MAC_CNTRL_1_IMPLICIT_BF_INT_CONF_LSB 28
+#define MAC_HW_MAC_CNTRL_1_IMPLICIT_BF_INT_CONF_WIDTH ((u32)0x00000002)
+#define MAC_HW_MAC_CNTRL_1_DISABLE_BFR_RESP_BIT ((u32)0x08000000)
+#define MAC_HW_MAC_CNTRL_1_DISABLE_BFR_RESP_POS 27
+#define MAC_HW_MAC_CNTRL_1_RX_RIFS_EN_BIT ((u32)0x04000000)
+#define MAC_HW_MAC_CNTRL_1_RX_RIFS_EN_POS 26
+#define MAC_HW_MAC_CNTRL_1_TSF_MGT_DISABLE_BIT ((u32)0x02000000)
+#define MAC_HW_MAC_CNTRL_1_TSF_MGT_DISABLE_POS 25
+#define MAC_HW_MAC_CNTRL_1_TSF_UPDATED_BY_SW_BIT ((u32)0x01000000)
+#define MAC_HW_MAC_CNTRL_1_TSF_UPDATED_BY_SW_POS 24
+#define MAC_HW_MAC_CNTRL_1_MAC_DETECT_UNDERRUN_EN_BIT ((u32)0x00400000)
+#define MAC_HW_MAC_CNTRL_1_MAC_DETECT_UNDERRUN_EN_POS 22
+#define MAC_HW_MAC_CNTRL_1_DISABLE_MU_CTS_RESP_BIT ((u32)0x00200000)
+#define MAC_HW_MAC_CNTRL_1_DISABLE_MU_CTS_RESP_POS 21
+#define MAC_HW_MAC_CNTRL_1_BQRP_RESP_BY_FW_BIT ((u32)0x00100000)
+#define MAC_HW_MAC_CNTRL_1_BQRP_RESP_BY_FW_POS 20
+#define MAC_HW_MAC_CNTRL_1_BSRP_RESP_BY_FW_BIT ((u32)0x00080000)
+#define MAC_HW_MAC_CNTRL_1_BSRP_RESP_BY_FW_POS 19
+#define MAC_HW_MAC_CNTRL_1_ENABLE_NORMAL_ACK_RESP_IN_HE_MU_W_TRIG_BIT ((u32)0x00040000)
+#define MAC_HW_MAC_CNTRL_1_ENABLE_NORMAL_ACK_RESP_IN_HE_MU_W_TRIG_POS 18
+#define MAC_HW_MAC_CNTRL_1_DISABLE_NORMAL_ACK_RESP_IN_HE_MU_WO_TRIG_BIT ((u32)0x00020000)
+#define MAC_HW_MAC_CNTRL_1_DISABLE_NORMAL_ACK_RESP_IN_HE_MU_WO_TRIG_POS 17
+#define MAC_HW_MAC_CNTRL_1_ABGN_MODE_MASK ((u32)0x0001C000)
+#define MAC_HW_MAC_CNTRL_1_ABGN_MODE_LSB 14
+#define MAC_HW_MAC_CNTRL_1_ABGN_MODE_WIDTH ((u32)0x00000003)
+#define MAC_HW_MAC_CNTRL_1_KEY_STO_RAM_RESET_BIT ((u32)0x00002000)
+#define MAC_HW_MAC_CNTRL_1_KEY_STO_RAM_RESET_POS 13
+#define MAC_HW_MAC_CNTRL_1_MIB_TABLE_RESET_BIT ((u32)0x00001000)
+#define MAC_HW_MAC_CNTRL_1_MIB_TABLE_RESET_POS 12
+#define MAC_HW_MAC_CNTRL_1_RATE_CONTROLLER_MPIF_BIT ((u32)0x00000800)
+#define MAC_HW_MAC_CNTRL_1_RATE_CONTROLLER_MPIF_POS 11
+#define MAC_HW_MAC_CNTRL_1_DISABLE_BA_RESP_BIT ((u32)0x00000400)
+#define MAC_HW_MAC_CNTRL_1_DISABLE_BA_RESP_POS 10
+#define MAC_HW_MAC_CNTRL_1_DISABLE_CTS_RESP_BIT ((u32)0x00000200)
+#define MAC_HW_MAC_CNTRL_1_DISABLE_CTS_RESP_POS 9
+#define MAC_HW_MAC_CNTRL_1_DISABLE_ACK_RESP_BIT ((u32)0x00000100)
+#define MAC_HW_MAC_CNTRL_1_DISABLE_ACK_RESP_POS 8
+#define MAC_HW_MAC_CNTRL_1_ACTIVE_CLK_GATING_BIT ((u32)0x00000080)
+#define MAC_HW_MAC_CNTRL_1_ACTIVE_CLK_GATING_POS 7
+#define MAC_HW_MAC_CNTRL_1_ENABLE_LP_CLK_SWITCH_BIT ((u32)0x00000040)
+#define MAC_HW_MAC_CNTRL_1_ENABLE_LP_CLK_SWITCH_POS 6
+#define MAC_HW_MAC_CNTRL_1_FORCE_MSTA_BA_BIT ((u32)0x00000020)
+#define MAC_HW_MAC_CNTRL_1_FORCE_MSTA_BA_POS 5
+#define MAC_HW_MAC_CNTRL_1_DISABLE_FAST_COMPARE_BIT ((u32)0x00000010)
+#define MAC_HW_MAC_CNTRL_1_DISABLE_FAST_COMPARE_POS 4
+#define MAC_HW_MAC_CNTRL_1_CFP_AWARE_BIT ((u32)0x00000008)
+#define MAC_HW_MAC_CNTRL_1_CFP_AWARE_POS 3
+#define MAC_HW_MAC_CNTRL_1_PWR_MGT_BIT ((u32)0x00000004)
+#define MAC_HW_MAC_CNTRL_1_PWR_MGT_POS 2
+#define MAC_HW_MAC_CNTRL_1_AP_BIT ((u32)0x00000002)
+#define MAC_HW_MAC_CNTRL_1_AP_POS 1
+#define MAC_HW_MAC_CNTRL_1_BSS_TYPE_BIT ((u32)0x00000001)
+#define MAC_HW_MAC_CNTRL_1_BSS_TYPE_POS 0
+
+static inline void mac_hw_mac_cntrl_1_active_clk_gating_setf(struct cl_hw *cl_hw, u8 activeclkgating)
+{
+ ASSERT_ERR((((u32)activeclkgating << 7) & ~((u32)0x00000080)) == 0);
+ cl_reg_write(cl_hw, MAC_HW_MAC_CNTRL_1_ADDR,
+ (cl_reg_read(cl_hw, MAC_HW_MAC_CNTRL_1_ADDR) & ~((u32)0x00000080)) | ((u32)activeclkgating << 7));
+}
+
+/*
+ * @brief EDCA_CCA_BUSY register definition
+ * Indicates the CCA busy time. register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31:00 CCA_BUSY_DUR 0x0
+ * </pre>
+ */
+#define MAC_HW_EDCA_CCA_BUSY_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000220)
+#define MAC_HW_EDCA_CCA_BUSY_OFFSET 0x00000220
+#define MAC_HW_EDCA_CCA_BUSY_INDEX 0x00000088
+#define MAC_HW_EDCA_CCA_BUSY_RESET 0x00000000
+
+static inline u32 mac_hw_edca_cca_busy_get(struct cl_hw *cl_hw)
+{
+ return cl_reg_read(cl_hw, MAC_HW_EDCA_CCA_BUSY_ADDR);
+}
+
+/*
+ * @brief RX_MINE_BUSY register definition
+ * RX Busy time by my frames counter register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31:00 rx_mine_time 0x0
+ * </pre>
+ */
+#define MAC_HW_RX_MINE_BUSY_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000234)
+#define MAC_HW_RX_MINE_BUSY_OFFSET 0x00000234
+#define MAC_HW_RX_MINE_BUSY_INDEX 0x0000008D
+#define MAC_HW_RX_MINE_BUSY_RESET 0x00000000
+
+static inline u32 mac_hw_rx_mine_busy_get(struct cl_hw *cl_hw)
+{
+ return cl_reg_read(cl_hw, MAC_HW_RX_MINE_BUSY_ADDR);
+}
+
+/*
+ * @brief TX_MINE_BUSY register definition
+ * TX BUSY time by my TX frames register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31:00 TX_MINE_TIME 0x0
+ * </pre>
+ */
+#define MAC_HW_TX_MINE_BUSY_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000238)
+#define MAC_HW_TX_MINE_BUSY_OFFSET 0x00000238
+#define MAC_HW_TX_MINE_BUSY_INDEX 0x0000008E
+#define MAC_HW_TX_MINE_BUSY_RESET 0x00000000
+
+static inline u32 mac_hw_tx_mine_busy_get(struct cl_hw *cl_hw)
+{
+ return cl_reg_read(cl_hw, MAC_HW_TX_MINE_BUSY_ADDR);
+}
+
+/*
+ * @brief EDCA_NAV_BUSY register definition
+ * Indicates the NAV busy time register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31:00 NAV_BUSY_DUR 0x0
+ * </pre>
+ */
+#define MAC_HW_EDCA_NAV_BUSY_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000248)
+#define MAC_HW_EDCA_NAV_BUSY_OFFSET 0x00000248
+#define MAC_HW_EDCA_NAV_BUSY_INDEX 0x00000092
+#define MAC_HW_EDCA_NAV_BUSY_RESET 0x00000000
+
+static inline u32 mac_hw_edca_nav_busy_get(struct cl_hw *cl_hw)
+{
+ return cl_reg_read(cl_hw, MAC_HW_EDCA_NAV_BUSY_ADDR);
+}
+
+/*
+ * @brief ADD_CCA_BUSY_SEC_20 register definition
+ * Indicates the CCA on Secondary 20MHz busy time. register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31:00 CCA_BUSY_DUR_SEC_20 0x0
+ * </pre>
+ */
+#define MAC_HW_ADD_CCA_BUSY_SEC_20_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000290)
+#define MAC_HW_ADD_CCA_BUSY_SEC_20_OFFSET 0x00000290
+#define MAC_HW_ADD_CCA_BUSY_SEC_20_INDEX 0x000000A4
+#define MAC_HW_ADD_CCA_BUSY_SEC_20_RESET 0x00000000
+
+static inline u32 mac_hw_add_cca_busy_sec_20_get(struct cl_hw *cl_hw)
+{
+ return cl_reg_read(cl_hw, MAC_HW_ADD_CCA_BUSY_SEC_20_ADDR);
+}
+
+/*
+ * @brief ADD_CCA_BUSY_SEC_40 register definition
+ * Indicates the CCA on Secondary 40MHz busy time. register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31:00 CCA_BUSY_DUR_SEC_40 0x0
+ * </pre>
+ */
+#define MAC_HW_ADD_CCA_BUSY_SEC_40_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000294)
+#define MAC_HW_ADD_CCA_BUSY_SEC_40_OFFSET 0x00000294
+#define MAC_HW_ADD_CCA_BUSY_SEC_40_INDEX 0x000000A5
+#define MAC_HW_ADD_CCA_BUSY_SEC_40_RESET 0x00000000
+
+static inline u32 mac_hw_add_cca_busy_sec_40_get(struct cl_hw *cl_hw)
+{
+ return cl_reg_read(cl_hw, MAC_HW_ADD_CCA_BUSY_SEC_40_ADDR);
+}
+
+/*
+ * @brief ADD_CCA_BUSY_SEC_80 register definition
+ * Indicates the CCA on Secondary 80MHz busy time. register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31:00 CCA_BUSY_DUR_SEC_80 0x0
+ * </pre>
+ */
+#define MAC_HW_ADD_CCA_BUSY_SEC_80_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000298)
+#define MAC_HW_ADD_CCA_BUSY_SEC_80_OFFSET 0x00000298
+#define MAC_HW_ADD_CCA_BUSY_SEC_80_INDEX 0x000000A6
+#define MAC_HW_ADD_CCA_BUSY_SEC_80_RESET 0x00000000
+
+static inline u32 mac_hw_add_cca_busy_sec_80_get(struct cl_hw *cl_hw)
+{
+ return cl_reg_read(cl_hw, MAC_HW_ADD_CCA_BUSY_SEC_80_ADDR);
+}
+
+/*
+ * @brief INTRA_BSS_NAV_BUSY register definition
+ * Count intra BSS NAV busy period register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31:00 INTRA_BSS_NAV_BUSY_DUR 0x0
+ * </pre>
+ */
+#define MAC_HW_INTRA_BSS_NAV_BUSY_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000408)
+#define MAC_HW_INTRA_BSS_NAV_BUSY_OFFSET 0x00000408
+#define MAC_HW_INTRA_BSS_NAV_BUSY_INDEX 0x00000102
+#define MAC_HW_INTRA_BSS_NAV_BUSY_RESET 0x00000000
+
+static inline u32 mac_hw_intra_bss_nav_busy_get(struct cl_hw *cl_hw)
+{
+ return cl_reg_read(cl_hw, MAC_HW_INTRA_BSS_NAV_BUSY_ADDR);
+}
+
+/*
+ * @brief INTER_BSS_NAV_BUSY register definition
+ * Count inter BSS NAV busy period register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31:00 INTER_BSS_NAV_BUSY_DUR 0x0
+ * </pre>
+ */
+#define MAC_HW_INTER_BSS_NAV_BUSY_ADDR (REG_MAC_HW_BASE_ADDR + 0x0000040C)
+#define MAC_HW_INTER_BSS_NAV_BUSY_OFFSET 0x0000040C
+#define MAC_HW_INTER_BSS_NAV_BUSY_INDEX 0x00000103
+#define MAC_HW_INTER_BSS_NAV_BUSY_RESET 0x00000000
+
+static inline u32 mac_hw_inter_bss_nav_busy_get(struct cl_hw *cl_hw)
+{
+ return cl_reg_read(cl_hw, MAC_HW_INTER_BSS_NAV_BUSY_ADDR);
+}
+
+/*
+ * @brief DEBUG_PORT_SEL_A register definition
+ * Used to multiplex different sets of signals on the debug pins. register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 15:08 DEBUG_PORT_SEL_1 0x0
+ * 07:00 DEBUG_PORT_SEL_0 0x0
+ * </pre>
+ */
+#define MAC_HW_DEBUG_PORT_SEL_A_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000510)
+#define MAC_HW_DEBUG_PORT_SEL_A_OFFSET 0x00000510
+#define MAC_HW_DEBUG_PORT_SEL_A_INDEX 0x00000144
+#define MAC_HW_DEBUG_PORT_SEL_A_RESET 0x00000000
+
+static inline u32 mac_hw_debug_port_sel_a_get(struct cl_hw *cl_hw)
+{
+ return cl_reg_read(cl_hw, MAC_HW_DEBUG_PORT_SEL_A_ADDR);
+}
+
+static inline void mac_hw_debug_port_sel_a_set(struct cl_hw *cl_hw, u32 value)
+{
+ cl_reg_write(cl_hw, MAC_HW_DEBUG_PORT_SEL_A_ADDR, value);
+}
+
+/*
+ * @brief DEBUG_PORT_SEL_B register definition
+ * Used to multiplex different sets of signals on the register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 15:08 DEBUG_PORT_SEL_3 0x0
+ * 07:00 DEBUG_PORT_SEL_2 0x0
+ * </pre>
+ */
+#define MAC_HW_DEBUG_PORT_SEL_B_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000530)
+#define MAC_HW_DEBUG_PORT_SEL_B_OFFSET 0x00000530
+#define MAC_HW_DEBUG_PORT_SEL_B_INDEX 0x0000014C
+#define MAC_HW_DEBUG_PORT_SEL_B_RESET 0x00000000
+
+static inline u32 mac_hw_debug_port_sel_b_get(struct cl_hw *cl_hw)
+{
+ return cl_reg_read(cl_hw, MAC_HW_DEBUG_PORT_SEL_B_ADDR);
+}
+
+static inline void mac_hw_debug_port_sel_b_set(struct cl_hw *cl_hw, u32 value)
+{
+ cl_reg_write(cl_hw, MAC_HW_DEBUG_PORT_SEL_B_ADDR, value);
+}
+
+/*
+ * @brief DEBUG_PORT_SEL_C register definition
+ * Used to multiplex different sets of signals on the register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 15:08 DEBUG_PORT_SEL_5 0x0
+ * 07:00 DEBUG_PORT_SEL_4 0x0
+ * </pre>
+ */
+#define MAC_HW_DEBUG_PORT_SEL_C_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000534)
+#define MAC_HW_DEBUG_PORT_SEL_C_OFFSET 0x00000534
+#define MAC_HW_DEBUG_PORT_SEL_C_INDEX 0x0000014D
+#define MAC_HW_DEBUG_PORT_SEL_C_RESET 0x00000000
+
+static inline u32 mac_hw_debug_port_sel_c_get(struct cl_hw *cl_hw)
+{
+ return cl_reg_read(cl_hw, MAC_HW_DEBUG_PORT_SEL_C_ADDR);
+}
+
+static inline void mac_hw_debug_port_sel_c_set(struct cl_hw *cl_hw, u32 value)
+{
+ cl_reg_write(cl_hw, MAC_HW_DEBUG_PORT_SEL_C_ADDR, value);
+}
+
+/*
+ * @brief DEBUG_PORT_EN register definition
+ * Used to determine which debug ports are enabled register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 05 EN5 0
+ * 04 EN4 0
+ * 03 EN3 0
+ * 02 EN2 0
+ * 01 EN1 0
+ * 00 EN0 0
+ * </pre>
+ */
+#define MAC_HW_DEBUG_PORT_EN_ADDR (REG_MAC_HW_BASE_ADDR + 0x00000538)
+#define MAC_HW_DEBUG_PORT_EN_OFFSET 0x00000538
+#define MAC_HW_DEBUG_PORT_EN_INDEX 0x0000014E
+#define MAC_HW_DEBUG_PORT_EN_RESET 0x00000000
+
+static inline u32 mac_hw_debug_port_en_get(struct cl_hw *cl_hw)
+{
+ return cl_reg_read(cl_hw, MAC_HW_DEBUG_PORT_EN_ADDR);
+}
+
+static inline void mac_hw_debug_port_en_set(struct cl_hw *cl_hw, u32 value)
+{
+ cl_reg_write(cl_hw, MAC_HW_DEBUG_PORT_EN_ADDR, value);
+}
+
+/*
+ * @brief DOZE_CNTRL_2 register definition
+ * Contains settings for controlling DOZE state. register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31 WAKE_UP_FROM_DOZE 0
+ * 00 WAKE_UP_SW 1
+ * </pre>
+ */
+#define MAC_HW_DOZE_CNTRL_2_ADDR (REG_MAC_HW_BASE_ADDR + 0x00008048)
+#define MAC_HW_DOZE_CNTRL_2_OFFSET 0x00008048
+#define MAC_HW_DOZE_CNTRL_2_INDEX 0x00002012
+#define MAC_HW_DOZE_CNTRL_2_RESET 0x00000001
+
+/* Field definitions */
+#define MAC_HW_DOZE_CNTRL_2_WAKE_UP_FROM_DOZE_BIT ((u32)0x80000000)
+#define MAC_HW_DOZE_CNTRL_2_WAKE_UP_FROM_DOZE_POS 31
+#define MAC_HW_DOZE_CNTRL_2_WAKE_UP_SW_BIT ((u32)0x00000001)
+#define MAC_HW_DOZE_CNTRL_2_WAKE_UP_SW_POS 0
+
+static inline void mac_hw_doze_cntrl_2_wake_up_sw_setf(struct cl_hw *cl_hw, u8 wakeupsw)
+{
+ ASSERT_ERR((((u32)wakeupsw << 0) & ~((u32)0x00000001)) == 0);
+ cl_reg_write(cl_hw, MAC_HW_DOZE_CNTRL_2_ADDR,
+ (cl_reg_read(cl_hw, MAC_HW_DOZE_CNTRL_2_ADDR) & ~((u32)0x00000001)) | ((u32)wakeupsw << 0));
+}
+
+/*
+ * @brief TSF_LO register definition
+ * Contains the TSF bits. register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31:00 TSF_TIMER_LOW 0x0
+ * </pre>
+ */
+#define MAC_HW_TSF_LO_ADDR (REG_MAC_HW_BASE_ADDR + 0x000080A4)
+#define MAC_HW_TSF_LO_OFFSET 0x000080A4
+#define MAC_HW_TSF_LO_INDEX 0x00002029
+#define MAC_HW_TSF_LO_RESET 0x00000000
+
+static inline u32 mac_hw_tsf_lo_get(struct cl_hw *cl_hw)
+{
+ return cl_reg_read(cl_hw, MAC_HW_TSF_LO_ADDR);
+}
+
+/*
+ * @brief TSF_HI register definition
+ * Contains the TSF bits. register description
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31:00 TSF_TIMER_HIGH 0x0
+ * </pre>
+ */
+#define MAC_HW_TSF_HI_ADDR (REG_MAC_HW_BASE_ADDR + 0x000080A8)
+#define MAC_HW_TSF_HI_OFFSET 0x000080A8
+#define MAC_HW_TSF_HI_INDEX 0x0000202A
+#define MAC_HW_TSF_HI_RESET 0x00000000
+
+static inline u32 mac_hw_tsf_hi_get(struct cl_hw *cl_hw)
+{
+ return cl_reg_read(cl_hw, MAC_HW_TSF_HI_ADDR);
+}
+
+#endif /*CL_REG_MAC_HW_H */
--
2.30.0
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