From: Viktor Barna <viktor.barna@xxxxxxxxxx>
(Part of the split. Please, take a look at the cover letter for more
details).
Signed-off-by: Viktor Barna <viktor.barna@xxxxxxxxxx>
---
.../net/wireless/celeno/cl8k/reg/reg_cmu.h | 379 ++++++++++++++++++
1 file changed, 379 insertions(+)
create mode 100644 drivers/net/wireless/celeno/cl8k/reg/reg_cmu.h
diff --git a/drivers/net/wireless/celeno/cl8k/reg/reg_cmu.h b/drivers/net/wireless/celeno/cl8k/reg/reg_cmu.h
new file mode 100644
index 000000000000..59428bf81e20
--- /dev/null
+++ b/drivers/net/wireless/celeno/cl8k/reg/reg_cmu.h
@@ -0,0 +1,379 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright(c) 2019-2021, Celeno Communications Ltd. */
+
+#ifndef CL_REG_CMU_H
+#define CL_REG_CMU_H
+
+#include <linux/types.h>
+#include "reg/reg_access.h"
+#include "chip.h"
+
+#define REG_CMU_BASE_ADDR 0x007C6000
+
+/*
+ * @brief CMU_CLK_EN register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31 spare_afe_gnrl_en 0
+ * 30 spare_sys_gnrl_en 0
+ * 27 spare_riu44_clk_en 0
+ * 26 spare_riu_clk_en 0
+ * 25 spare_riu2x_clk_en 0
+ * 24 spare_riu4x_clk_en 0
+ * 23 spare_phy_clk_en 0
+ * 22 spare_phy2x_clk_en 0
+ * 21 spare_sysx_clk_en 0
+ * 20 spare_sys2x_clk_en 0
+ * 19 ricu_clk_en 0
+ * 05 smac_proc_clk_en 1
+ * 04 umac_proc_clk_en 1
+ * 03 lmac_proc_clk_en 1
+ * </pre>
+ */
+#define CMU_CLK_EN_ADDR (REG_CMU_BASE_ADDR + 0x00000000)
+#define CMU_CLK_EN_OFFSET 0x00000000
+#define CMU_CLK_EN_INDEX 0x00000000
+#define CMU_CLK_EN_RESET 0x00000038
+
+/* Field definitions */
+#define CMU_SPARE_AFE_GNRL_EN_BIT ((u32)0x80000000)
+#define CMU_SPARE_AFE_GNRL_EN_POS 31
+#define CMU_SPARE_SYS_GNRL_EN_BIT ((u32)0x40000000)
+#define CMU_SPARE_SYS_GNRL_EN_POS 30
+#define CMU_SPARE_RIU_44_CLK_EN_BIT ((u32)0x08000000)
+#define CMU_SPARE_RIU_44_CLK_EN_POS 27
+#define CMU_SPARE_RIU_CLK_EN_BIT ((u32)0x04000000)
+#define CMU_SPARE_RIU_CLK_EN_POS 26
+#define CMU_SPARE_RIU_2_X_CLK_EN_BIT ((u32)0x02000000)
+#define CMU_SPARE_RIU_2_X_CLK_EN_POS 25
+#define CMU_SPARE_RIU_4_X_CLK_EN_BIT ((u32)0x01000000)
+#define CMU_SPARE_RIU_4_X_CLK_EN_POS 24
+#define CMU_SPARE_PHY_CLK_EN_BIT ((u32)0x00800000)
+#define CMU_SPARE_PHY_CLK_EN_POS 23
+#define CMU_SPARE_PHY_2_X_CLK_EN_BIT ((u32)0x00400000)
+#define CMU_SPARE_PHY_2_X_CLK_EN_POS 22
+#define CMU_SPARE_SYSX_CLK_EN_BIT ((u32)0x00200000)
+#define CMU_SPARE_SYSX_CLK_EN_POS 21
+#define CMU_SPARE_SYS_2_X_CLK_EN_BIT ((u32)0x00100000)
+#define CMU_SPARE_SYS_2_X_CLK_EN_POS 20
+#define CMU_RICU_CLK_EN_BIT ((u32)0x00080000)
+#define CMU_RICU_CLK_EN_POS 19
+#define CMU_SMAC_PROC_CLK_EN_BIT ((u32)0x00000020)
+#define CMU_SMAC_PROC_CLK_EN_POS 5
+#define CMU_UMAC_PROC_CLK_EN_BIT ((u32)0x00000010)
+#define CMU_UMAC_PROC_CLK_EN_POS 4
+#define CMU_LMAC_PROC_CLK_EN_BIT ((u32)0x00000008)
+#define CMU_LMAC_PROC_CLK_EN_POS 3
+
+#define CMU_MAC_ALL_CLK_EN \
+ (CMU_RICU_CLK_EN_BIT | \
+ CMU_SMAC_PROC_CLK_EN_BIT | \
+ CMU_UMAC_PROC_CLK_EN_BIT | \
+ CMU_LMAC_PROC_CLK_EN_BIT)
+
+static inline void cmu_clk_en_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, CMU_CLK_EN_ADDR, value);
+}
+
+/*
+ * @brief CMU_PHY_0_CLK_EN register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 02 ceva0_clk_en 0
+ * 01 phy0_apb_clk_en 0
+ * 00 phy0_main_clk_en 0
+ * </pre>
+ */
+#define CMU_PHY_0_CLK_EN_ADDR (REG_CMU_BASE_ADDR + 0x00000004)
+#define CMU_PHY_0_CLK_EN_OFFSET 0x00000004
+#define CMU_PHY_0_CLK_EN_INDEX 0x00000001
+#define CMU_PHY_0_CLK_EN_RESET 0x00000000
+
+static inline void cmu_phy_0_clk_en_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, CMU_PHY_0_CLK_EN_ADDR, value);
+}
+
+/* Field definitions */
+#define CMU_CEVA_0_CLK_EN_BIT ((u32)0x00000004)
+#define CMU_CEVA_0_CLK_EN_POS 2
+#define CMU_PHY_0_APB_CLK_EN_BIT ((u32)0x00000002)
+#define CMU_PHY_0_APB_CLK_EN_POS 1
+#define CMU_PHY_0_MAIN_CLK_EN_BIT ((u32)0x00000001)
+#define CMU_PHY_0_MAIN_CLK_EN_POS 0
+
+#define CMU_PHY0_CLK_EN \
+ (CMU_CEVA_0_CLK_EN_BIT | \
+ CMU_PHY_0_APB_CLK_EN_BIT | \
+ CMU_PHY_0_MAIN_CLK_EN_BIT)
+
+static inline void cmu_phy_0_clk_en_pack(struct cl_chip *chip, u8 ceva0clken, u8 phy0apbclken,
+ u8 phy0mainclken)
+{
+ ASSERT_ERR_CHIP((((u32)ceva0clken << 2) & ~((u32)0x00000004)) == 0);
+ ASSERT_ERR_CHIP((((u32)phy0apbclken << 1) & ~((u32)0x00000002)) == 0);
+ ASSERT_ERR_CHIP((((u32)phy0mainclken << 0) & ~((u32)0x00000001)) == 0);
+ cl_reg_write_chip(chip, CMU_PHY_0_CLK_EN_ADDR, ((u32)ceva0clken << 2) |
+ ((u32)phy0apbclken << 1) | ((u32)phy0mainclken << 0));
+}
+
+static inline void cmu_phy_0_clk_en_ceva_0_clk_en_setf(struct cl_chip *chip, u8 ceva0clken)
+{
+ ASSERT_ERR_CHIP((((u32)ceva0clken << 2) & ~((u32)0x00000004)) == 0);
+ cl_reg_write_chip(chip, CMU_PHY_0_CLK_EN_ADDR,
+ (cl_reg_read_chip(chip, CMU_PHY_0_CLK_EN_ADDR) & ~((u32)0x00000004)) | ((u32)ceva0clken << 2));
+}
+
+static inline void cmu_phy_0_clk_en_phy_0_apb_clk_en_setf(struct cl_chip *chip, u8 phy0apbclken)
+{
+ ASSERT_ERR_CHIP((((u32)phy0apbclken << 1) & ~((u32)0x00000002)) == 0);
+ cl_reg_write_chip(chip, CMU_PHY_0_CLK_EN_ADDR,
+ (cl_reg_read_chip(chip, CMU_PHY_0_CLK_EN_ADDR) & ~((u32)0x00000002)) | ((u32)phy0apbclken << 1));
+}
+
+/*
+ * @brief CMU_PHY_1_CLK_EN register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 02 ceva1_clk_en 0
+ * 01 phy1_apb_clk_en 0
+ * 00 phy1_main_clk_en 0
+ * </pre>
+ */
+#define CMU_PHY_1_CLK_EN_ADDR (REG_CMU_BASE_ADDR + 0x00000008)
+#define CMU_PHY_1_CLK_EN_OFFSET 0x00000008
+#define CMU_PHY_1_CLK_EN_INDEX 0x00000002
+#define CMU_PHY_1_CLK_EN_RESET 0x00000000
+
+static inline void cmu_phy_1_clk_en_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, CMU_PHY_1_CLK_EN_ADDR, value);
+}
+
+/* Field definitions */
+#define CMU_CEVA_1_CLK_EN_BIT ((u32)0x00000004)
+#define CMU_CEVA_1_CLK_EN_POS 2
+#define CMU_PHY_1_APB_CLK_EN_BIT ((u32)0x00000002)
+#define CMU_PHY_1_APB_CLK_EN_POS 1
+#define CMU_PHY_1_MAIN_CLK_EN_BIT ((u32)0x00000001)
+#define CMU_PHY_1_MAIN_CLK_EN_POS 0
+
+#define CMU_PHY1_CLK_EN \
+ (CMU_CEVA_1_CLK_EN_BIT | \
+ CMU_PHY_1_APB_CLK_EN_BIT | \
+ CMU_PHY_1_MAIN_CLK_EN_BIT)
+
+static inline void cmu_phy_1_clk_en_pack(struct cl_chip *chip, u8 ceva1clken, u8 phy1apbclken,
+ u8 phy1mainclken)
+{
+ ASSERT_ERR_CHIP((((u32)ceva1clken << 2) & ~((u32)0x00000004)) == 0);
+ ASSERT_ERR_CHIP((((u32)phy1apbclken << 1) & ~((u32)0x00000002)) == 0);
+ ASSERT_ERR_CHIP((((u32)phy1mainclken << 0) & ~((u32)0x00000001)) == 0);
+ cl_reg_write_chip(chip, CMU_PHY_1_CLK_EN_ADDR, ((u32)ceva1clken << 2) |
+ ((u32)phy1apbclken << 1) | ((u32)phy1mainclken << 0));
+}
+
+static inline void cmu_phy_1_clk_en_ceva_1_clk_en_setf(struct cl_chip *chip, u8 ceva1clken)
+{
+ ASSERT_ERR_CHIP((((u32)ceva1clken << 2) & ~((u32)0x00000004)) == 0);
+ cl_reg_write_chip(chip, CMU_PHY_1_CLK_EN_ADDR,
+ (cl_reg_read_chip(chip, CMU_PHY_1_CLK_EN_ADDR) & ~((u32)0x00000004)) | ((u32)ceva1clken << 2));
+}
+
+static inline void cmu_phy_1_clk_en_phy_1_apb_clk_en_setf(struct cl_chip *chip, u8 phy1apbclken)
+{
+ ASSERT_ERR_CHIP((((u32)phy1apbclken << 1) & ~((u32)0x00000002)) == 0);
+ cl_reg_write_chip(chip, CMU_PHY_1_CLK_EN_ADDR,
+ (cl_reg_read_chip(chip, CMU_PHY_1_CLK_EN_ADDR) & ~((u32)0x00000002)) | ((u32)phy1apbclken << 1));
+}
+
+/*
+ * @brief CMU_CONTROL register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 00 gl_mux_sel 0
+ * </pre>
+ */
+#define CMU_CONTROL_ADDR (REG_CMU_BASE_ADDR + 0x0000000C)
+#define CMU_CONTROL_OFFSET 0x0000000C
+#define CMU_CONTROL_INDEX 0x00000003
+#define CMU_CONTROL_RESET 0x00000000
+
+static inline void cmu_control_gl_mux_sel_setf(struct cl_chip *chip, u8 glmuxsel)
+{
+ ASSERT_ERR_CHIP((((u32)glmuxsel << 0) & ~((u32)0x00000001)) == 0);
+ cl_reg_write_chip(chip, CMU_CONTROL_ADDR, (u32)glmuxsel << 0);
+}
+
+/*
+ * @brief CMU_RST register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 18 spare_riu44_reset_n 0
+ * 17 spare_modem_reset_n 0
+ * 16 spare_sys_reset_n 0
+ * 15 n_RICURst 1
+ * </pre>
+ */
+#define CMU_RST_ADDR (REG_CMU_BASE_ADDR + 0x00000010)
+#define CMU_RST_OFFSET 0x00000010
+#define CMU_RST_INDEX 0x00000004
+#define CMU_RST_RESET 0x0000FF80
+
+static inline void cmu_rst_n_ricurst_setf(struct cl_chip *chip, u8 nricurst)
+{
+ ASSERT_ERR_CHIP((((u32)nricurst << 15) & ~((u32)0x00008000)) == 0);
+ cl_reg_write_chip(chip, CMU_RST_ADDR,
+ (cl_reg_read_chip(chip, CMU_RST_ADDR) & ~((u32)0x00008000)) | ((u32)nricurst << 15));
+}
+
+/*
+ * @brief CMU_PHY_0_RST register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 03 ceva0_global_rst_n 1
+ * 02 mpif0_rst_n 1
+ * 01 phy0_preset_n 1
+ * 00 phy0_rst_n 1
+ * </pre>
+ */
+#define CMU_PHY_0_RST_ADDR (REG_CMU_BASE_ADDR + 0x00000014)
+#define CMU_PHY_0_RST_OFFSET 0x00000014
+#define CMU_PHY_0_RST_INDEX 0x00000005
+#define CMU_PHY_0_RST_RESET 0x0000000F
+
+static inline void cmu_phy_0_rst_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, CMU_PHY_0_RST_ADDR, value);
+}
+
+/* Field definitions */
+#define CMU_CEVA_0_GLOBAL_RST_N_BIT ((u32)0x00000008)
+#define CMU_CEVA_0_GLOBAL_RST_N_POS 3
+#define CMU_MPIF_0_RST_N_BIT ((u32)0x00000004)
+#define CMU_MPIF_0_RST_N_POS 2
+#define CMU_PHY_0_PRESET_N_BIT ((u32)0x00000002)
+#define CMU_PHY_0_PRESET_N_POS 1
+#define CMU_PHY_0_RST_N_BIT ((u32)0x00000001)
+#define CMU_PHY_0_RST_N_POS 0
+
+#define CMU_PHY0_RST_EN \
+ (CMU_PHY_0_PRESET_N_BIT | \
+ CMU_MPIF_0_RST_N_BIT | \
+ CMU_PHY_0_RST_N_BIT | \
+ CMU_CEVA_0_GLOBAL_RST_N_BIT)
+
+static inline void cmu_phy_0_rst_ceva_0_global_rst_n_setf(struct cl_chip *chip, u8 ceva0globalrstn)
+{
+ ASSERT_ERR_CHIP((((u32)ceva0globalrstn << 3) & ~((u32)0x00000008)) == 0);
+ cl_reg_write_chip(chip, CMU_PHY_0_RST_ADDR,
+ (cl_reg_read_chip(chip, CMU_PHY_0_RST_ADDR) & ~((u32)0x00000008)) | ((u32)ceva0globalrstn << 3));
+}
+
+/*
+ * @brief CMU_PHY_1_RST register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 03 ceva1_global_rst_n 1
+ * 02 mpif1_rst_n 1
+ * 01 phy1_preset_n 1
+ * 00 phy1_rst_n 1
+ * </pre>
+ */
+#define CMU_PHY_1_RST_ADDR (REG_CMU_BASE_ADDR + 0x00000018)
+#define CMU_PHY_1_RST_OFFSET 0x00000018
+#define CMU_PHY_1_RST_INDEX 0x00000006
+#define CMU_PHY_1_RST_RESET 0x0000000F
+
+static inline void cmu_phy_1_rst_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, CMU_PHY_1_RST_ADDR, value);
+}
+
+/* Field definitions */
+#define CMU_CEVA_1_GLOBAL_RST_N_BIT ((u32)0x00000008)
+#define CMU_CEVA_1_GLOBAL_RST_N_POS 3
+#define CMU_MPIF_1_RST_N_BIT ((u32)0x00000004)
+#define CMU_MPIF_1_RST_N_POS 2
+#define CMU_PHY_1_PRESET_N_BIT ((u32)0x00000002)
+#define CMU_PHY_1_PRESET_N_POS 1
+#define CMU_PHY_1_RST_N_BIT ((u32)0x00000001)
+#define CMU_PHY_1_RST_N_POS 0
+
+#define CMU_PHY1_RST_EN \
+ (CMU_PHY_1_PRESET_N_BIT | \
+ CMU_MPIF_1_RST_N_BIT | \
+ CMU_PHY_1_RST_N_BIT | \
+ CMU_CEVA_1_GLOBAL_RST_N_BIT)
+
+static inline void cmu_phy_1_rst_ceva_1_global_rst_n_setf(struct cl_chip *chip, u8 ceva1globalrstn)
+{
+ ASSERT_ERR_CHIP((((u32)ceva1globalrstn << 3) & ~((u32)0x00000008)) == 0);
+ cl_reg_write_chip(chip, CMU_PHY_1_RST_ADDR,
+ (cl_reg_read_chip(chip, CMU_PHY_1_RST_ADDR) & ~((u32)0x00000008)) | ((u32)ceva1globalrstn << 3));
+}
+
+/*
+ * @brief CMU_PLL_1_STAT register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 31 pll_lock 0
+ * </pre>
+ */
+#define CMU_PLL_1_STAT_ADDR (REG_CMU_BASE_ADDR + 0x00000050)
+#define CMU_PLL_1_STAT_OFFSET 0x00000050
+#define CMU_PLL_1_STAT_INDEX 0x00000014
+#define CMU_PLL_1_STAT_RESET 0x00000000
+
+static inline u8 cmu_pll_1_stat_pll_lock_getf(struct cl_chip *chip)
+{
+ u32 local_val = cl_reg_read_chip(chip, CMU_PLL_1_STAT_ADDR);
+
+ ASSERT_ERR_CHIP((local_val & ~((u32)0x80000000)) == 0);
+ return (local_val >> 31);
+}
+
+/*
+ * @brief CMU_PHASE_SEL register definition
+ * <pre>
+ * Bits Field Name Reset Value
+ * ----- ------------------ -----------
+ * 20 gp_clk_phase_sel 1
+ * 19 dac_cdb_clk_phase_sel 0
+ * 18 adc_cdb_clk_phase_sel 0
+ * 17 dac_clk_phase_sel 0
+ * 16 adc_clk_phase_sel 0
+ * </pre>
+ */
+#define CMU_PHASE_SEL_ADDR (REG_CMU_BASE_ADDR + 0x00000060)
+#define CMU_PHASE_SEL_OFFSET 0x00000060
+#define CMU_PHASE_SEL_INDEX 0x00000018
+#define CMU_PHASE_SEL_RESET 0x00100000
+
+static inline void cmu_phase_sel_set(struct cl_chip *chip, u32 value)
+{
+ cl_reg_write_chip(chip, CMU_PHASE_SEL_ADDR, value);
+}
+
+/* Field definitions */
+#define CMU_GP_CLK_PHASE_SEL_BIT ((u32)0x00100000)
+#define CMU_GP_CLK_PHASE_SEL_POS 20
+#define CMU_DAC_CDB_CLK_PHASE_SEL_BIT ((u32)0x00080000)
+#define CMU_DAC_CDB_CLK_PHASE_SEL_POS 19
+#define CMU_ADC_CDB_CLK_PHASE_SEL_BIT ((u32)0x00040000)
+#define CMU_ADC_CDB_CLK_PHASE_SEL_POS 18
+#define CMU_DAC_CLK_PHASE_SEL_BIT ((u32)0x00020000)
+#define CMU_DAC_CLK_PHASE_SEL_POS 17
+#define CMU_ADC_CLK_PHASE_SEL_BIT ((u32)0x00010000)
+#define CMU_ADC_CLK_PHASE_SEL_POS 16
+
+#endif /* CL_REG_CMU_H */
--
2.30.0
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