From: Viktor Barna <viktor.barna@xxxxxxxxxx>
(Part of the split. Please, take a look at the cover letter for more
details).
Signed-off-by: Viktor Barna <viktor.barna@xxxxxxxxxx>
---
drivers/net/wireless/celeno/cl8k/chip.h | 143 ++++++++++++++++++++++++
1 file changed, 143 insertions(+)
create mode 100644 drivers/net/wireless/celeno/cl8k/chip.h
diff --git a/drivers/net/wireless/celeno/cl8k/chip.h b/drivers/net/wireless/celeno/cl8k/chip.h
new file mode 100644
index 000000000000..c7548ca92e59
--- /dev/null
+++ b/drivers/net/wireless/celeno/cl8k/chip.h
@@ -0,0 +1,143 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright(c) 2019-2021, Celeno Communications Ltd. */
+
+#ifndef CL_CHIP_H
+#define CL_CHIP_H
+
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#ifdef CONFIG_CL_PCIE
+#include <linux/pci.h>
+#endif
+#include "calib.h"
+#include "temperature.h"
+#include "bus/pci/ipc.h"
+#include "chip_config.h"
+
+/**
+ * DOC: Chip basics
+ *
+ * Each physical device of ours is a separate chip, that is being described by
+ * %cl_chip structure. Each chip may be several (%TCV_MAX) transceivers (bands),
+ * which are operating simultaneously and are described via own %ieee80211_hw
+ * unit (it refers to the private driver via specific pointer, described by
+ * %cl_hw). Totally, 3 types of bands are supported - 2.4G/5.2G/6G. Driver
+ * supports multiple chips (up to %CHIP_MAX). Since the driver can control up
+ * to %TCV_TOTAL entities, it is important to pass it's pointer to each
+ * function, that operates somehow with specific band/transceiver.
+ *
+ * Chip instance is being created during bus probing procedure and is being
+ * destroyed during bus removal procedure.
+ *
+ * Physically, 80xx chips family may have different amount of antennas (4/6/8),
+ * each of which may not be hardly bounded to the specific band (both bands are
+ * sharing them and may change antenna combinations in specific circumstances).
+ *
+ * Each band (transceiver) has own FW, that is being loaded by
+ * request_firmware() call during chip structure initialization procedure. At
+ * lower layer each band is associated with own HW die by LMAC and SMAC names
+ * (e.g: 5.2G and 2.4G). Celeno is using XMAC naming when we are referring to any
+ * of LMAC/SMAC components.
+ */
+
+enum cl_bus_type {
+ CL_BUS_TYPE_PCI,
+};
+
+struct cl_irq_stats {
+ unsigned long last_rx;
+ unsigned long last_tx;
+ unsigned long last_isr;
+ u32 last_isr_statuses;
+ u32 count_irq;
+ u32 ipc_success;
+};
+
+struct cl_fem_params {
+ u8 wiring_id;
+ u16 lut[FEM_TYPE_MAX];
+ u16 lut_registers[TCV_MAX][FEM_LUT_AMOUNT_PER_MAC];
+ u16 lut_off_register[TCV_MAX];
+ u16 lut_off_register_list[FEM_TYPE_MAX];
+};
+
+struct cl_afe_reg {
+ u32 ctrl36_phy0;
+ u32 ctrl36_phy1;
+ u32 ctrl37_phy0;
+ u32 ctrl37_phy1;
+};
+
+struct cl_ring_indices {
+ struct cl_ipc_ring_indices *params;
+ dma_addr_t dma_addr;
+ struct dma_pool *pool;
+};
+
+struct cl_xmem {
+ u32 total_used;
+ u32 size;
+};
+
+struct cl_ela_db {
+ char *raw_lcu_config;
+ struct list_head cmd_head;
+ struct {
+ u32 adaptations_cnt;
+ u32 applications_cnt;
+ } stats;
+ int error_state;
+};
+
+struct cl_chip {
+ u8 idx;
+ enum cl_bus_type bus_type;
+ bool temperature_configured;
+ u8 max_antennas;
+#ifdef CONFIG_CL_PCIE
+ struct pci_driver pci_drv;
+ struct pci_dev *pci_dev;
+#endif
+ void __iomem *pci_bar0_virt_addr;
+ struct cl_irq_stats irq_stats;
+ struct cl_temperature temperature;
+ struct cl_chip_conf *conf;
+ struct device *dev;
+ struct cl_hw *cl_hw_lut[TCV_MAX];
+ struct cl_hw *cl_hw_tcv0;
+ struct cl_hw *cl_hw_tcv1;
+ spinlock_t isr_lock;
+ spinlock_t spi_lock;
+ rwlock_t cl_hw_lock;
+ bool fw_first_tcv;
+ struct cl_fem_params fem;
+ struct eeprom *eeprom_cache;
+ int (*eeprom_read_block)(struct cl_chip *chip, u16 addr, u16 num_of_byte, u8 *data);
+ int (*eeprom_write_block)(struct cl_chip *chip, u16 addr, u16 num_of_byte, u8 *data);
+ struct cl_afe_reg orig_afe_reg;
+ u8 agc_table_entry;
+ u8 lna_bypass_mode_set;
+ struct cl_calib_db calib_db;
+ struct cl_ela_db ela_db;
+ struct cl_ring_indices ring_indices;
+ u8 reg_dbg;
+ struct cl_xmem xmem_db;
+};
+
+struct cl_chip *cl_chip_alloc(u8 idx);
+void cl_chip_dealloc(struct cl_chip *chip);
+int cl_chip_init(struct cl_chip *chip);
+void cl_chip_deinit(struct cl_chip *chip);
+bool cl_chip_is_enabled(struct cl_chip *chip);
+bool cl_chip_is_both_enabled(struct cl_chip *chip);
+bool cl_chip_is_tcv_enabled(struct cl_chip *chip, u8 tcv_idx);
+bool cl_chip_is_tcv0_enabled(struct cl_chip *chip);
+bool cl_chip_is_tcv1_enabled(struct cl_chip *chip);
+void cl_chip_set_hw(struct cl_chip *chip, struct cl_hw *cl_hw);
+void cl_chip_unset_hw(struct cl_chip *chip, struct cl_hw *cl_hw);
+bool cl_chip_is_8ant(struct cl_chip *chip);
+bool cl_chip_is_6ant(struct cl_chip *chip);
+bool cl_chip_is_4ant(struct cl_chip *chip);
+bool cl_chip_is_6g(struct cl_chip *chip);
+
+#endif /* CL_CHIP_H */
--
2.30.0
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