On Thu, Apr 25, 2019 at 09:50:20AM +0200, Thomas Gleixner wrote:
> On Wed, 24 Apr 2019, Fenghua Yu wrote:
> >
> > +static void split_lock_update_msr(void)
> > +{
> > + /* Enable split lock detection */
> > + msr_set_bit(MSR_TEST_CTL, TEST_CTL_SPLIT_LOCK_DETECT_SHIFT);
> > + this_cpu_or(msr_test_ctl_cache, TEST_CTL_SPLIT_LOCK_DETECT);
>
> I'm pretty sure, that I told you to utilize the cache proper. Again:
>
> > > Nothing in this file initializes msr_test_ctl_cache explicitely. Register
> > > caching always requires to read the register and store it in the cache
> > > before doing anything with it. Nothing guarantees that all bits in that MSR
> > > are 0 by default forever.
> > >
> > > And once you do that _before_ calling split_lock_update_msr() then you can
> > > spare the RMW in that function.
>
> So you managed to fix the initializaiton part, but then you still do a
> pointless RMW.
Ok. I see. msr_set_bit() is a RMW operation.
So is the following the right code to update msr and cache variable?
+static void split_lock_update_msr(void)
+{
+ /* Enable split lock detection */
+ this_cpu_or(msr_test_ctl_cache, TEST_CTL_SPLIT_LOCK_DETECT);
+ wrmsrl(MSR_TEST_CTL, msr_test_ctl_cache);
Thanks.
-Fenghua
