* Fenghua Yu <fenghua.yu@xxxxxxxxx> wrote: > A new MSR_IA32_CORE_CAPABILITY (0xcf) is defined. Each bit in the MSR > enumerates a model specific feature. Currently bit 5 enumerates split > lock detection. When bit 5 is 1, split lock detection is supported. > When the bit is 0, split lock detection is not supported. > > Please check the latest Intel 64 and IA-32 Architectures Software > Developer's Manual for more detailed information on the MSR and the > split lock detection bit. > > Signed-off-by: Fenghua Yu <fenghua.yu@xxxxxxxxx> > --- > arch/x86/include/asm/msr-index.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > index ca5bc0eacb95..f65ef6f783d2 100644 > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -59,6 +59,9 @@ > #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 > #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) > > +#define MSR_IA32_CORE_CAPABILITY 0x000000cf > +#define CORE_CAP_SPLIT_LOCK_DETECT BIT(5) /* Detect split lock */ Please don't put comments into definitions. Thanks, Ingo
