Erik Stromdahl <erik.stromdahl@xxxxxxxxx> writes: > From: Alagu Sankar <alagusankar@xxxxxxxxxxxxxxx> > > HTC header carries junk values that may be interpreted by the firmware > differently. Enable credit update only if flow control is enabled for > the corresponding endpoint. > > PLL clock setting sequence does not mask the PLL_CONTROL > register value. Side effect of not masking the values is not known as > the entire pll clock setting sequence is undocumented. One logical change per patch, please. So this should be split to two. > Signed-off-by: Alagu Sankar <alagusankar@xxxxxxxxxxxxxxx> Erik's s-o-b missing. > --- a/drivers/net/wireless/ath/ath10k/hw.c > +++ b/drivers/net/wireless/ath/ath10k/hw.c > @@ -814,6 +814,8 @@ static int ath10k_hw_qca6174_enable_pll_clock(struct ath10k *ar) > if (ret) > return -EINVAL; > > + reg_val &= ~(WLAN_PLL_CONTROL_REFDIV_MASK | WLAN_PLL_CONTROL_DIV_MASK | > + WLAN_PLL_CONTROL_NOPWD_MASK); > reg_val |= (SM(hw_clk->refdiv, WLAN_PLL_CONTROL_REFDIV) | > SM(hw_clk->div, WLAN_PLL_CONTROL_DIV) | > SM(1, WLAN_PLL_CONTROL_NOPWD)); The commit log mentions that there are no visible changes after this patch. So why add it? :) And do note that this also changes functionality for QCA6174 and QCA9377 PCI devices, so we have to be careful here. -- Kalle Valo
