From: Chien-Hsun Liao <ben.liao@xxxxxxxxxxx> After writing a rf register, driver should wait for several microseconds. If we write a rf register and read it immediately without a delay, we could get a wrong value because the writing is not finished yet. Based on the simulation results, writing a rf register by pi write needs 13 microsenconds, writing rf register directly write needs 1 microsecond to complete. And modify direct write flow to make sure that there is no hardware pi write simultaneously. Signed-off-by: Chien-Hsun Liao <ben.liao@xxxxxxxxxxx> Signed-off-by: Yan-Hsuan Chuang <yhchuang@xxxxxxxxxxx> --- drivers/net/wireless/realtek/rtw88/phy.c | 10 ++++++++++ drivers/net/wireless/realtek/rtw88/reg.h | 4 ++++ 2 files changed, 14 insertions(+) diff --git a/drivers/net/wireless/realtek/rtw88/phy.c b/drivers/net/wireless/realtek/rtw88/phy.c index ae066e6..6cb07b5 100644 --- a/drivers/net/wireless/realtek/rtw88/phy.c +++ b/drivers/net/wireless/realtek/rtw88/phy.c @@ -5,6 +5,7 @@ #include <linux/bcd.h> #include "main.h" +#include "reg.h" #include "fw.h" #include "phy.h" #include "debug.h" @@ -573,6 +574,8 @@ bool rtw_phy_write_rf_reg_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, rtw_write32(rtwdev, sipi_addr[rf_path], data_and_addr); + udelay(13); + return true; } @@ -593,8 +596,15 @@ bool rtw_phy_write_rf_reg(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, direct_addr = base_addr[rf_path] + (addr << 2); mask &= RFREG_MASK; + rtw_write32_mask(rtwdev, REG_RSV_CTRL, BITS_RFC_DIRECT, DISABLE_PI); + rtw_write32_mask(rtwdev, REG_WLRF1, BITS_RFC_DIRECT, DISABLE_PI); rtw_write32_mask(rtwdev, direct_addr, mask, data); + udelay(1); + + rtw_write32_mask(rtwdev, REG_RSV_CTRL, BITS_RFC_DIRECT, ENABLE_PI); + rtw_write32_mask(rtwdev, REG_WLRF1, BITS_RFC_DIRECT, ENABLE_PI); + return true; } diff --git a/drivers/net/wireless/realtek/rtw88/reg.h b/drivers/net/wireless/realtek/rtw88/reg.h index 05424ec..304c8df 100644 --- a/drivers/net/wireless/realtek/rtw88/reg.h +++ b/drivers/net/wireless/realtek/rtw88/reg.h @@ -14,6 +14,9 @@ #define BIT_CPU_CLK_EN BIT(14) #define REG_RSV_CTRL 0x001C +#define DISABLE_PI 0x3 +#define ENABLE_PI 0x2 +#define BITS_RFC_DIRECT (BIT(31) | BIT(30)) #define BIT_WLMCU_IOIF BIT(0) #define REG_RF_CTRL 0x001F #define BIT_RF_SDM_RSTB BIT(2) @@ -66,6 +69,7 @@ BIT_CHECK_SUM_OK) #define FW_READY_MASK 0xffff +#define REG_WLRF1 0x00EC #define REG_SYS_CFG1 0x00F0 #define BIT_RTL_ID BIT(23) #define BIT_RF_TYPE_ID BIT(27) -- 2.7.4
