On 11 April 2018 at 15:37, Daniel Mack <daniel@xxxxxxxxxx> wrote: > Hi Loic, > > On Wednesday, April 11, 2018 03:30 PM, Loic Poulain wrote: >>> /* Move the head of the ring to the next empty descriptor */ >>> - ch->head_blk_ctl = ctl->next; >>> + ch->head_blk_ctl = ctl_skb->next; >>> + >>> + /* Commit all previous writes and set descriptors to VALID */ >>> + wmb(); >> >> Is this first memory barrier really needed? from what I understand, we >> only need to ensure that the control descriptor is marked valid at the >> end of the procedure and we don't really care about the paylod one. > > Well, without documentation or the firmware sources, that's just > guesswork at this point. My assumption is only based on the weird > comments and workarounds in the downstream driver. > > I added the second barrier to ensure that no descriptor is ever marked > valid unless all other bits are definitely in sync. Fair enough!
