The tech committee would like to announce a new accepted talk. Arkadi Sharshevski will give a talk on the new dpipe tool. Details are as follows: ----- While doing the hardware offloading process much of the hardware specifics cannot be presented. One example for such is the routing LPM algorithm used in Mellanox Spectrum ASIC which differs in hardware implementation from the kernel software implementation. The only information the user receives is whether specific route is offloaded or not, but he cannot really understand the underlying implementation nor get the specific statistics related to that process. Another example is TC classification-action offload which in hardware commonly implemented using TCAM memory. Currently there is no capability to gain visibility into the TCAM structure and to debug sub-optimal resource allocation. The new dpipe interface introduces capability for exporting the ASICs pipeline abstraction via devlink infrastructure, which should serve as an complementary tool. This infrastructure allows the user to get visibility into the ASIC by modeling it as a set of match/action tables. ----- cheers, jamal
