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Re: [RFC] ath10k: implement dql for htt tx

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On 03/30/2016 02:22 AM, Michal Kazior wrote:
On 29 March 2016 at 17:54, Ben Greear <greearb@xxxxxxxxxxxxxxx> wrote:
On 03/29/2016 12:49 AM, Michal Kazior wrote:

if you are getting a pure codel result of 160ms, that means the
implementation is broken. But I think (after having read your
description twice), the baseline result today of 160ms of queuing was
with a fq_codel *qdisc* doing the work on top of huge buffers,


Yes. The 160ms is with fq_codel qdisc with ath10k doing DQL at 6mbps.
Without DQL ath10k would clog up all tx slots (1424 of them) with
frames. At 6mbps you typically want/need a handful (5-10) of frames to
be queued.


Have you actually verified you can use all tx slots?

It works in most cases. I guess you're suspecting some of your
tx(flushing?) problems might be induced by overcommiting?

The way the
firmware uses it's tx buffers I think you may not be able to actually
do that...and in practice, you will get a lot fewer usable tx-buffers
than configured....

Could be, e.g. I'm aware management frames are kind of a special case
in recent firmware revisions.

What would/do you expect firmware would/will do when we overcommit?
The driver does advertise number of HTT tx slots so I would expect it
to work fine if it didn't crash during boot.

The firmware will return something like tx-dropped immediately.  The reason
is that the firmware keeps more than one internal priority queue, and in general, reserves
some of the tx-descriptors for high priority.

So, you never see tx-queues completely full in the driver, so tx queues are
not stopped farther up the stack.

Possibly I am confused about some of this, so I'm quite curious if you ever see
tx-queues determined to be full in the ath10k driver.

Thanks,
Ben

--
Ben Greear <greearb@xxxxxxxxxxxxxxx>
Candela Technologies Inc  http://www.candelatech.com

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