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Re: About adding support for MT76x2U to Linux kernel

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On Tue, Mar 08, 2016 at 01:58:03PM +0100, Felix Fietkau wrote:
> On 2016-03-08 13:49, Johannes Stezenbach wrote:
> > On Mon, Mar 07, 2016 at 10:22:38PM +0100, Felix Fietkau wrote:
> >> On 2016-03-07 13:41, Johannes Stezenbach wrote:
> >> > http://www.mediatek.com/en/downloads1/downloads/mt7612u/
> >> I checked, they simply use a software timer for it and stuff buffered
> >> multicast packets into the BE queue. I don't think the hardware offers
> >> any better way of doing this...
> > 
> > I had to refresh my memory on this driver.  The thing that tripped
> > me when I first read through it was that is using a jiffies based
> > timer and additionally sets it to fire 10ms after the calculated
> > beacon time.  So it's always too late, isn't it?
> > 
> > But of course it is irrelevant for us since we can use a hrtimer.
> > However, if other frames are queued in the hw they are still sent
> > before the buffered frames.  Since the hw has a dedicated queue
> > for HCCA I wonder if it could be used here?
> > (My knowledged of the standard is also rusty, ISTR the buffered
> > traffic must be sent before other traffic before the stations
> > go back to sleep.)
> On mt76x2e, I simply use the management queue for buffered frames, since
> it has a very high priority, and management frames are typically
> delivered via the voice WMM queue anyway.
> I think the MAC is probably similar enough that the same approach is
> possible on mt76x2u as well.

The mt7610u has 2 IN and 6 OUT endpoints, where 1 IN and 1 out
are for MCU commands and the 5 remaining OUT EPs are
for EDCA VO/VI/BE/BK and HCCA.

I found the vendor driver uses:

#define MGMTPIPEIDX				0	/* EP6 is highest priority */

where the comment is confusing since

#define EDCA_AC0_PIPE	0	/* Bulk EP1 OUT */
#define EDCA_AC1_PIPE	1	/* Bulk EP2 OUT */
#define EDCA_AC2_PIPE	2	/* Bulk EP3	OUT */
#define	EDCA_AC3_PIPE	3	/* Bulk EP4 OUT */
#define	HCCA_PIPE		4	/* Bulk EP5	OUT */



Johannes
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