Vasanthakumar Thiagarajan <vthiagar@xxxxxxxxxxxxxxxx> writes: > It is observed that during cold reset pcie access right > after a write operation to SOC_GLOBAL_RESET_ADDRESS causes > Data Bus Error and system hard lockup. The reason > for bus error is that pcie needs some time to get > back to stable state for any transaction during cold reset. Add > delay of 20 msecs after write of SOC_GLOBAL_RESET_ADDRESS > to fix this issue. This patch is tested on QCA988X. This is > also tested on QCA99X0 which is WIP. > > Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@xxxxxxxxxxxxxxxx> Thanks, applied. -- Kalle Valo -- To unsubscribe from this list: send the line "unsubscribe linux-wireless" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
