On 02/02/2015 10:54 AM, Johannes Berg wrote:
On Mon, 2015-02-02 at 09:33 -0800, Peter Oh wrote:
The code (as it is before your patch) implies that it's trying to make
sure that before it continues, any previous writes to the PCIe
device's
registers are posted. The only way to ensure that is to do a read to
the
registers, as the code does now.
Do you know how the read ensure that although the read code does not
check the return value?
Can you explain how a read ensures that posted write reaches PCIe
device?
You basically have the following sequence:
iowrite()
ioread()
If you look, you'll see that iowrite() is actually done (or should be,
or perhaps with appropriate syncs) on an uncached mapping.
since it's mmio, iowrite will be map to write, not out which is cached
mapping.
That's why we address "posted write" here.
If it's un-cached mapping which is volatile, we don't even need ioread.
As a result,
the only thing you care about here is the PCIe bus, not the CPU cache
flush. And from there on that's just a question of PCIe bus semantics.
So how does ioread guarantee PCIe bus transaction done?
johannes
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Regards,
Peter
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