On Mon, Dec 08, 2014 at 12:55:38PM +0000, Johannes Stezenbach wrote: > On Fri, Dec 05, 2014 at 06:53:03PM +0000, Catalin Marinas wrote: > > On Fri, Dec 05, 2014 at 06:39:45PM +0000, Catalin Marinas wrote: > > > > > > Does your system have an L2 cache? What's the SoC topology, can PCIe see > > > such L2 cache (or snoop the L1 caches)? > > > > BTW, if you really have a PL310-like L2 cache, have a look at some > > patches (I've seen similar symptoms) and make sure your configuration is > > correct: > > > > http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=6395/1 > > > > http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=6529/1 > > > > The first one is vexpress specific. The second one was eventually > > discarded by Russell (I don't remember the reason, I guess it's because > > SoC code is supposed to set the right bits in there anyway). In your > > case, such bits may be set up by firmware, so Linux cannot fix anything > > up. > > How do you avoid the unpredictable behavior mentioned in the > PL310 TRM when the Shared Attribute Invalidate Enable bit is set? > http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246h/Ceggcfcj.html So you talk about "Shared Attribute _Invalidate_ Enable" (bit 13) while I talk about "Shared Attribute _Override_ Enable" (bit 22). In addition, Shared _Invalidate_ behaviour can only be enabled if Shared Attribute _Override_ Enable bit is not set. -- Catalin -- To unsubscribe from this list: send the line "unsubscribe linux-wireless" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
