On Mon, Nov 13, 2023 at 03:43:47PM +0000, Daniel Golle wrote:
> Add support for watchdog and reset generator unit of the MediaTek
> MT7988 SoC.
>
> Signed-off-by: Daniel Golle <daniel@xxxxxxxxxxxxxx>
Reviewed-by: Guenter Roeck <linux@xxxxxxxxxxxx>
> ---
> v2: call new toprgu_reset_sw_en_unlocked from toprgu_reset_update while
> holding lock.
>
> drivers/watchdog/mtk_wdt.c | 40 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
> index b2330b16b497a..5a31a8746e954 100644
> --- a/drivers/watchdog/mtk_wdt.c
> +++ b/drivers/watchdog/mtk_wdt.c
> @@ -58,6 +58,8 @@
> #define WDT_SWSYSRST 0x18U
> #define WDT_SWSYS_RST_KEY 0x88000000
>
> +#define WDT_SWSYSRST_EN 0xfc
> +
> #define DRV_NAME "mtk-wdt"
> #define DRV_VERSION "1.0"
>
> @@ -71,10 +73,12 @@ struct mtk_wdt_dev {
> struct reset_controller_dev rcdev;
> bool disable_wdt_extrst;
> bool reset_by_toprgu;
> + bool has_swsysrst_en;
> };
>
> struct mtk_wdt_data {
> int toprgu_sw_rst_num;
> + bool has_swsysrst_en;
> };
>
> static const struct mtk_wdt_data mt2712_data = {
> @@ -89,6 +93,11 @@ static const struct mtk_wdt_data mt7986_data = {
> .toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM,
> };
>
> +static const struct mtk_wdt_data mt7988_data = {
> + .toprgu_sw_rst_num = 24,
> + .has_swsysrst_en = true,
> +};
> +
> static const struct mtk_wdt_data mt8183_data = {
> .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
> };
> @@ -109,6 +118,28 @@ static const struct mtk_wdt_data mt8195_data = {
> .toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM,
> };
>
> +/**
> + * toprgu_reset_sw_en_unlocked() - enable/disable software control for reset bit
> + * @mtk_wdt: Pointer to instance of struct mtk_wdt_dev.
> + * @id: Bit number identifying the reset to be enabled or disabled.
> + * @enable: If true, enable software control for that bit, disable otherwise.
> + *
> + * Context: The caller must hold lock of struct mtk_wdt_dev.
> + */
> +static void toprgu_reset_sw_en_unlocked(struct mtk_wdt_dev *data,
> + unsigned long id, bool enable)
> +{
> + u32 tmp;
> +
> + tmp = readl(data->wdt_base + WDT_SWSYSRST_EN);
> + if (enable)
> + tmp |= BIT(id);
> + else
> + tmp &= ~BIT(id);
> +
> + writel(tmp, data->wdt_base + WDT_SWSYSRST_EN);
> +}
> +
> static int toprgu_reset_update(struct reset_controller_dev *rcdev,
> unsigned long id, bool assert)
> {
> @@ -119,6 +150,9 @@ static int toprgu_reset_update(struct reset_controller_dev *rcdev,
>
> spin_lock_irqsave(&data->lock, flags);
>
> + if (assert && data->has_swsysrst_en)
> + toprgu_reset_sw_en_unlocked(data, id, true);
> +
> tmp = readl(data->wdt_base + WDT_SWSYSRST);
> if (assert)
> tmp |= BIT(id);
> @@ -127,6 +161,9 @@ static int toprgu_reset_update(struct reset_controller_dev *rcdev,
> tmp |= WDT_SWSYS_RST_KEY;
> writel(tmp, data->wdt_base + WDT_SWSYSRST);
>
> + if (!assert && data->has_swsysrst_en)
> + toprgu_reset_sw_en_unlocked(data, id, false);
> +
> spin_unlock_irqrestore(&data->lock, flags);
>
> return 0;
> @@ -406,6 +443,8 @@ static int mtk_wdt_probe(struct platform_device *pdev)
> wdt_data->toprgu_sw_rst_num);
> if (err)
> return err;
> +
> + mtk_wdt->has_swsysrst_en = wdt_data->has_swsysrst_en;
> }
>
> mtk_wdt->disable_wdt_extrst =
> @@ -444,6 +483,7 @@ static const struct of_device_id mtk_wdt_dt_ids[] = {
> { .compatible = "mediatek,mt6589-wdt" },
> { .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data },
> { .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data },
> + { .compatible = "mediatek,mt7988-wdt", .data = &mt7988_data },
> { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
> { .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data },
> { .compatible = "mediatek,mt8188-wdt", .data = &mt8188_data },
> --
> 2.42.1
