Hi Guenter, hi Wim, hi Hanspeter, On Mon, 2023-10-16 at 15:16 +0200, Werner Fischer wrote: > Hi Guenter, hi Hanspeter, > > I currently testing two devices with IT8784 and IT8786 watchdog > timers. > Although the chips are supported by it87_wdt.c after Hanspeter's > patches back in 2020, the watchdog functionality does not work in my > following test: > - Debian 12 using Kernel 6.1.58 or current 6.6-rc > - loading module it87_wdt > - starting wd_keepalive Deamon > - killing wd_keepalive using signal 9 > -> system keeps on running even after the configured watchdog timeout > > For debugging purposes, I have used the patch below to report the > content of the watchdog registers 0x71 (WDTCTRL), 0x72 (WDTCFG), 0x73 > (WDTVALLSB), and 0x74 (WDTVALMSB) to the system log. > > It turned out, that 0x71 (WDTCTRL) has initially the following value > set (before the module changes it to 0x00): > - 8 decimal (IT8784 / IT8786) > - 4 decimal (IT8613) > > I figured out, that the following code line makes the watchdog of > IT8784 and IT8786 non-functional for me: > superio_outb(0x00, WDTCTRL); > I have removed this code in my patch below, then the watchdog works > for IT8784 and IT8786. > > I'm not sure, why the WDTCTRL register is set to 0x00 in the code. As > it seems, the register can have different meanings for differnt > IT8xxx chips. Accoring to [1] it seems sufficient to set both > WDTVALLSB and WDTVALMSB to 0x00 to deactivate the watchdog timer: > "When the WDT Time-out Value register is set to a non-zero value, the > WDT loads the value and begin counting down from the value." > This happens e.g. also when wd_keepalive is stopped cleanly. > > I am open to support to improve the it87_wdt code. > > But before I'm writing and sending a patch, I have the following > question: > * What is the reason, why WDTCTRL is set to 0x00 in the code? and > * Could we think about removing this (at least for IT8784/8786)? It seems to me that setting WDTCTRL to 0x00 has been in the code from the beginning. For my test systems with IT8784 and IT8786 I got the following information from the system vendor: "71H bit 3 is the mode choice for the clock input of the IT8784/IT8786 chip. This bit is set to 1 (= PCICLK mode) and can not be set to 0." Setting it to 0 breaks the watchdog functionality. Unfortunately, ITE does not provide the specifications PDFs publicly anymore. But the documentation at [2] provides details regarding the Watchdog Timer Control Register (71h) of an ITE chip, which has the description "External CLK_IN Select: 1: PCICLK" for bit 3, too. As it seems system-dependent, removing superio_outb(0x00, WDTCTRL); from the code may lead to problems with other ITE chips, which maybe could need WDTCTRL set to 0x00. So my idea to be on the safe side for exiting users of it87_wdt, too: * What do you think about an optional module parameter to let the user choose to leave WDTCTRL untouched? (this would make the watchdog work e.g. with my test systems with IT8784 and IT8786, too) In case you would support such a code change, I would be happy to write a patch (including some other minor/cosmetic code fixes/addition of further ITE chips). Best regards, Werner [2] http://files.nexcom.com/Driver/NDiSB425/User_Manual_NDiSB425-SI3_170111.pdf
