On 05/10/2023 17:56, Peter Griffin wrote: > CMU_TOP is the top level clock management unit which contains PLLs, muxes > and gates that feed the other clock management units. > > Signed-off-by: Peter Griffin <peter.griffin@xxxxxxxxxx> > --- > drivers/clk/samsung/Kconfig | 9 + > drivers/clk/samsung/Makefile | 1 + > drivers/clk/samsung/clk-gs101.c | 1558 +++++++++++++++++++++++++++++++ > 3 files changed, 1568 insertions(+) > create mode 100644 drivers/clk/samsung/clk-gs101.c > > diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig > index 76a494e95027..4c8f173c4dec 100644 > --- a/drivers/clk/samsung/Kconfig > +++ b/drivers/clk/samsung/Kconfig > @@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG > select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420 > select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS > select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD > + select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR Let's put it before Tesla. There's not much order, but maybe one day we will fix it. > > config S3C64XX_COMMON_CLK > bool "Samsung S3C64xx clock controller support" if COMPILE_TEST > @@ -102,3 +103,11 @@ config TESLA_FSD_COMMON_CLK > help > Support for the clock controller present on the Tesla FSD SoC. > Choose Y here only if you build for this SoC. > + > +config GOOGLE_GS101_COMMON_CLK Let's put it before Tesla. > + bool "Google gs101 clock controller support" if COMPILE_TEST > + depends on COMMON_CLK_SAMSUNG > + depends on EXYNOS_ARM64_COMMON_CLK > + help > + Support for the clock controller present on the Google gs101 SoC. > + Choose Y here only if you build for this SoC. > \ No newline at end of file Missing newline > diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile > index ebbeacabe88f..1e69b8e14324 100644 > --- a/drivers/clk/samsung/Makefile > +++ b/drivers/clk/samsung/Makefile > @@ -24,3 +24,4 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o > obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o > obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o > obj-$(CONFIG_TESLA_FSD_COMMON_CLK) += clk-fsd.o > +obj-$(CONFIG_GOOGLE_GS101_COMMON_CLK) += clk-gs101.o Before S3C64xx > diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c > new file mode 100644 > index 000000000000..4c58fcc899be > --- /dev/null > +++ b/drivers/clk/samsung/clk-gs101.c > @@ -0,0 +1,1558 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2023 Linaro Ltd. > + * Author: Peter Griffin <peter.griffin@xxxxxxxxxx> > + * > + * Common Clock Framework support for GS101. > + */ > + ... > + /* PERI1 */ > + GATE(CLK_GOUT_PERIC1_BUS, "gout_cmu_peric1_bus", "mout_cmu_peric1_bus", > + CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 21, 0, 0), > + GATE(CLK_GOUT_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip", > + CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0), > + > + /* TPU */ > + GATE(CLK_GOUT_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu", > + CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0), > + GATE(CLK_GOUT_TPU_TPUCTL, "gout_cmu_tpu_tpuctl", "mout_cmu_tpu_tpuctl", > + CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 21, 0, 0), > + GATE(CLK_GOUT_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus", > + CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0), > + GATE(CLK_GOUT_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart", > + CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0), > + > + /* BO */ > + GATE(CLK_GOUT_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus", > + CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0), > + stray blank line Best regards, Krzysztof
