On Sat, Sep 23, 2023 at 04:34:38PM +0200, Jonathan Neuschäfer wrote: > This driver implements the following features w.r.t. the clock and reset > controller in the WPCM450 SoC: > > - It calculates the rates for all clocks managed by the clock controller > - It leaves the clock tree mostly unchanged, except that it enables/ > disables clock gates based on usage. > - It exposes the reset lines managed by the controller using the > Generic Reset Controller subsystem > > NOTE: If the driver and the corresponding devicetree node are present, > the driver will disable "unused" clocks. This is problem until > the clock relations are properly declared in the devicetree (in a > later patch). Until then, the clk_ignore_unused kernel parameter > can be used as a workaround. > > Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@xxxxxxx> > Reviewed-by: Joel Stanley <joel@xxxxxxxxx> > --- [...] > +config CLK_WPCM450 > + bool "Nuvoton WPCM450 clock/reset controller support" > + default y > + help > + Build the clock and reset controller driver for the WPCM450 SoC. > + [...] > config RESET_SIMPLE > bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT > - default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC > + default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC || ARCH_WPCM450 Considering the build bot failures and the fragility of adding tons of platforms to this "default" line, I think I'll just select RESET_CONTROLLER and RESET_SIMPLE from CLK_WPCM450. Jonathan
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