On Wed, 8 Mar 2023 at 04:42, Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx> wrote:
>
> Add watchdog node for the StarFive JH7100 RISC-V SoC.
>
> Signed-off-by: Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx>
> ---
> arch/riscv/boot/dts/starfive/jh7100.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
> index 000447482aca..1eb7c21a94fd 100644
> --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
> @@ -238,5 +238,15 @@ i2c3: i2c@12460000 {
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + wdog: watchdog@12480000 {
I don't see anything referencing this node, so the label can be dropped.
With that fixed:
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@xxxxxxxxxxxxx>
> + compatible = "starfive,jh7100-wdt";
> + reg = <0x0 0x12480000 0x0 0x10000>;
> + clocks = <&clkgen JH7100_CLK_WDTIMER_APB>,
> + <&clkgen JH7100_CLK_WDT_CORE>;
> + clock-names = "apb", "core";
> + resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
> + <&rstgen JH7100_RSTN_WDT>;
> + };
> };
> };
> --
> 2.25.1
>
>
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