On 10/06/2022 09:57, Geert Uytterhoeven wrote:
>> "+ cpu0: cpu@0 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a35";
>> + clocks = <&clk NPCM8XX_CLK_CPU>;
>> + reg = <0x0 0x0>;
>> Why do you have two address cells? A bit more complicated and not
>> necessary, I think."
>> the arm,cortex-a35 is 64 Bit this is why we use #address-cells = <2>;
>> and therefore reg = <0x0 0x0>;
>
> These addresses are not addresses on the main memory bus (which
> is indeed 64-bit), but on the logical CPU bus.
> Now, Documentation/devicetree/bindings/arm/cpus.yaml says you can
> have #address-cells = <2> if you have non-zero MPIDR_EL1 high bits.
>
Thanks Tomer and Geert for explanation. OK for me.
Best regards,
Krzysztof
