Hi Terry, On Sun, 30 Jan 2022 12:41:30 -0600, Terry Bowman wrote: > Enable EFCH MMIO using check for SMBus PCI revision ID value 0x51 or > greater. SMBus PCI revision ID 0x51 is first used by family 17h. This > PCI revision ID check will also enable future AMD processors with the > same EFCH SMBus controller HW. > > Signed-off-by: Terry Bowman <terry.bowman@xxxxxxx> > --- > drivers/i2c/busses/i2c-piix4.c | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c > index c5325cadaf55..6a9495d994bc 100644 > --- a/drivers/i2c/busses/i2c-piix4.c > +++ b/drivers/i2c/busses/i2c-piix4.c > @@ -101,6 +101,8 @@ > #define SB800_PIIX4_FCH_PM_ADDR 0xFED80300 > #define SB800_PIIX4_FCH_PM_SIZE 8 > > +#define AMD_PCI_SMBUS_REVISION_MMIO 0x51 > + I don't think that was worth a define. You only use the value once, in a context where the symbolic name doesn't add much value IMHO. -- Jean Delvare SUSE L3 Support
