On Wed, May 12, 2021 at 02:17:23PM +0530, shruthi.sanil@xxxxxxxxx wrote: > From: Shruthi Sanil <shruthi.sanil@xxxxxxxxx> > > Updated the WDT SMC handler MACRO name to make it clear that its > a ARM SMC handler that helps in clearing the WDT interrupt bit. > > Tested-by: Kris Pan <kris.pan@xxxxxxxxx> > Signed-off-by: Shruthi Sanil <shruthi.sanil@xxxxxxxxx> Reviewed-by: Guenter Roeck <linux@xxxxxxxxxxxx> > --- > drivers/watchdog/keembay_wdt.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/watchdog/keembay_wdt.c b/drivers/watchdog/keembay_wdt.c > index 63a7c5d719a3..0a8cf5b35699 100644 > --- a/drivers/watchdog/keembay_wdt.c > +++ b/drivers/watchdog/keembay_wdt.c > @@ -25,7 +25,7 @@ > > #define WDT_TH_INT_MASK BIT(8) > #define WDT_TO_INT_MASK BIT(9) > -#define WDT_ISR_CLEAR 0x8200ff18 > +#define WDT_INT_CLEAR_SMC 0x8200ff18 > #define WDT_UNLOCK 0xf1d0dead > #define WDT_DISABLE 0x0 > #define WDT_ENABLE 0x1 > @@ -143,7 +143,7 @@ static irqreturn_t keembay_wdt_to_isr(int irq, void *dev_id) > struct keembay_wdt *wdt = dev_id; > struct arm_smccc_res res; > > - arm_smccc_smc(WDT_ISR_CLEAR, WDT_TO_INT_MASK, 0, 0, 0, 0, 0, 0, &res); > + arm_smccc_smc(WDT_INT_CLEAR_SMC, WDT_TO_INT_MASK, 0, 0, 0, 0, 0, 0, &res); > dev_crit(wdt->wdd.parent, "Intel Keem Bay non-sec wdt timeout.\n"); > emergency_restart(); > > @@ -157,7 +157,7 @@ static irqreturn_t keembay_wdt_th_isr(int irq, void *dev_id) > > keembay_wdt_set_pretimeout(&wdt->wdd, 0x0); > > - arm_smccc_smc(WDT_ISR_CLEAR, WDT_TH_INT_MASK, 0, 0, 0, 0, 0, 0, &res); > + arm_smccc_smc(WDT_INT_CLEAR_SMC, WDT_TH_INT_MASK, 0, 0, 0, 0, 0, 0, &res); > dev_crit(wdt->wdd.parent, "Intel Keem Bay non-sec wdt pre-timeout.\n"); > watchdog_notify_pretimeout(&wdt->wdd); > > -- > 2.17.1 >
